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Pseudo-Random Number Generators in VHDL
5 Commits 1 Branch 0 Tags 84 KiB
VHDL 82.1%
C 8.3%
C++ 7.7%
Makefile 1.9%
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Joris van Rantwijk b498a1e543 Rename entity xoroshiro128 and change interface. 
* Rename to rng_xoroshiro128plus
 * Change interface to valid/ready-based stream (not tested).
 		2016-10-21 13:12:02 +02:00
refimpl Add Makefile for software reference code. 2016-10-21 12:01:30 +02:00
rtl Rename entity xoroshiro128 and change interface. 2016-10-21 13:12:02 +02:00
sim Initial commit: 2016-10-21 11:31:26 +02:00