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Rename entities of top-level synthesis wrappers. 

Two entities named 'top' causes problems for the synthesizer.
This commit is contained in:
Joris van Rantwijk 2016-11-12 23:01:49 +01:00
parent 500d8e8b2a
commit 8cf9ca1673
2 changed files with 6 additions and 6 deletions
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6
synth/top_mt19937.vhdl
View File

@ -2,16 +2,16 @@
library ieee;
use ieee.std_logic_1164.all;
entity top is
entity topmt is
port (
clk : in std_logic;
rst : in std_logic;
ready: in std_logic;
valid: out std_logic;
data: out std_logic_vector(31 downto 0) );
end top;
end topmt;
architecture arch of top is
architecture arch of topmt is
begin
inst_prng: entity work.rng_mt19937

6
synth/top_xoroshiro.vhdl
View File

@ -2,16 +2,16 @@
library ieee;
use ieee.std_logic_1164.all;
entity top is
entity topxs is
port (
clk : in std_logic;
rst : in std_logic;
ready: in std_logic;
valid: out std_logic;
data: out std_logic_vector(63 downto 0) );
end top;
end topxs;
architecture arch of top is
architecture arch of topxs is
begin
inst_prng: entity work.rng_xoroshiro128plus