52 lines
906 B
VHDL
52 lines
906 B
VHDL
--
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-- Pair of flip-flops located in adjacent slices.
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--
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library ieee;
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use ieee.std_logic_1164.all;
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entity ffpair is
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port (
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-- Clocks.
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clk1: in std_logic;
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clk2: in std_logic;
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-- Input data, synchronous to "clk1".
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di: in std_logic;
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-- Output data, synchronous to "clk2";
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do: out std_logic
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);
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end entity;
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architecture rtl of ffpair is
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signal reg1: std_logic;
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signal reg2: std_logic;
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attribute RLOC: string;
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attribute RLOC of reg1: signal is "X0Y0";
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attribute RLOC of reg2: signal is "X1Y0";
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begin
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process (clk1) is
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begin
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if rising_edge(clk1) then
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reg1 <= di;
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end if;
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end process;
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process (clk2) is
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begin
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if rising_edge(clk2) then
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reg2 <= reg1;
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end if;
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end process;
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do <= reg2;
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end architecture;
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