redpitaya-puzzlefw/fpga/rtl/ffpair.vhd

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VHDL
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2024-10-08 08:49:34 +02:00
--
-- Pair of flip-flops located in adjacent slices.
--
library ieee;
use ieee.std_logic_1164.all;
entity ffpair is
port (
-- Clocks.
clk1: in std_logic;
clk2: in std_logic;
-- Input data, synchronous to "clk1".
di: in std_logic;
-- Output data, synchronous to "clk2";
do: out std_logic
);
end entity;
architecture rtl of ffpair is
signal reg1: std_logic;
signal reg2: std_logic;
attribute RLOC: string;
attribute RLOC of reg1: signal is "X0Y0";
attribute RLOC of reg2: signal is "X1Y0";
begin
process (clk1) is
begin
if rising_edge(clk1) then
reg1 <= di;
end if;
end process;
process (clk2) is
begin
if rising_edge(clk2) then
reg2 <= reg1;
end if;
end process;
do <= reg2;
end architecture;