Joris van Rantwijk c14441ffd1 Clean up FPGA gitignore		2024-09-21 20:20:12 +02:00
..
constraints	Set PULLDOWN on digital inputs	2024-08-29 10:03:00 +02:00
rtl	Add register bit to show 4-channel support	2024-09-18 20:59:31 +02:00
vivado	Add timetagger logic	2024-08-30 23:04:02 +02:00
.gitignore	Clean up FPGA gitignore	2024-09-21 20:20:12 +02:00
01_get_redpitaya.sh	Update block design and Vivado project	2024-08-27 22:40:01 +02:00
11_build_bitfile.sh	Log synthesizer messages to file	2024-08-30 23:04:27 +02:00
script_env	Script to build bitfile	2024-08-03 13:14:19 +02:00