redpitaya-puzzlefw/fpga/rtl
Joris van Rantwijk b445abd149 Double internal RAM for 4-input board
Double the size of the RAM buffer before DMA for analog sample data.
This makes room for 16k samples in 4-channel mode
(or 32k samples in 2-channel mode).
2024-10-10 21:17:21 +02:00
..
acquisition_chain.vhd Add external trigger-once mode 2024-09-24 20:51:02 +02:00
acquisition_manager.vhd Read digital input signals 2024-08-27 23:48:12 +02:00
acquisition_stream.vhd Fix 2-channel mode for 4-channel board 2024-10-09 23:06:12 +02:00
adc_capture.vhd Test analog acquisition chain 2024-08-26 21:31:55 +02:00
adc_capture_ddr.vhd Add support for 4-input Red Pitaya 2024-10-08 08:49:34 +02:00
adc_range_monitor.vhd Add monitoring of ADC sample and min/max range 2024-08-26 23:11:16 +02:00
adc_sample_stream.vhd Test analog acquisition chain 2024-08-26 21:31:55 +02:00
deglitch.vhd Read digital input signals 2024-08-27 23:48:12 +02:00
dma_axi_master.vhd Rework DMA to support single-beat transfers 2024-08-24 23:04:35 +02:00
dma_write_channel.vhd Add timetagger logic 2024-08-30 23:04:02 +02:00
ffpair.vhd Add support for 4-input Red Pitaya 2024-10-08 08:49:34 +02:00
puzzlefw_pkg.vhd Double internal RAM for 4-input board 2024-10-10 21:17:21 +02:00
puzzlefw_top.vhd Capture digital input via IDDR 2024-10-08 17:34:05 +02:00
puzzlefw_top_4ch.vhd Double internal RAM for 4-input board 2024-10-10 21:17:21 +02:00
registers.vhd Add external trigger-once mode 2024-09-24 20:51:02 +02:00
sample_decimation.vhd Test analog acquisition chain 2024-08-26 21:31:55 +02:00
shift_engine.vhd Test analog acquisition chain 2024-08-26 21:31:55 +02:00
simple_fifo.vhd Add timetagger logic 2024-08-30 23:04:02 +02:00
syncdff.vhd Read digital input signals 2024-08-27 23:48:12 +02:00
timestamp_gen.vhd Test analog acquisition chain 2024-08-26 21:31:55 +02:00
timetagger.vhd Delay timetagger signal to match ADC trigger 2024-09-22 15:01:25 +02:00
trigger_detector.vhd Add external trigger-once mode 2024-09-24 20:51:02 +02:00