255 lines
11 KiB
Tcl
255 lines
11 KiB
Tcl
#
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# $Id: red_pitaya.xdc 961 2014-01-21 11:40:39Z matej.oblak $
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#
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# @brief Red Pitaya location constraints.
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#
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# @Author Matej Oblak
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#
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# (c) Red Pitaya http://www.redpitaya.com
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#
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# Modified by Joris van Rantwijk for PuzzleFW.
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#
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############################################################################
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# IO constraints #
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############################################################################
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### ADC
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# ADC data
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set_property IOSTANDARD LVCMOS18 [get_ports {adc_dat_i[*][*]}]
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set_property IOB TRUE [get_ports {adc_dat_i[*][*]}]
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# ADC 0 data
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set_property PACKAGE_PIN V17 [get_ports {adc_dat_i[0][0]}]
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set_property PACKAGE_PIN U17 [get_ports {adc_dat_i[0][1]}]
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set_property PACKAGE_PIN Y17 [get_ports {adc_dat_i[0][2]}]
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set_property PACKAGE_PIN W16 [get_ports {adc_dat_i[0][3]}]
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set_property PACKAGE_PIN Y16 [get_ports {adc_dat_i[0][4]}]
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set_property PACKAGE_PIN W15 [get_ports {adc_dat_i[0][5]}]
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set_property PACKAGE_PIN W14 [get_ports {adc_dat_i[0][6]}]
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set_property PACKAGE_PIN Y14 [get_ports {adc_dat_i[0][7]}]
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set_property PACKAGE_PIN W13 [get_ports {adc_dat_i[0][8]}]
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set_property PACKAGE_PIN V12 [get_ports {adc_dat_i[0][9]}]
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set_property PACKAGE_PIN V13 [get_ports {adc_dat_i[0][10]}]
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set_property PACKAGE_PIN T14 [get_ports {adc_dat_i[0][11]}]
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set_property PACKAGE_PIN T15 [get_ports {adc_dat_i[0][12]}]
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set_property PACKAGE_PIN V15 [get_ports {adc_dat_i[0][13]}]
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set_property PACKAGE_PIN T16 [get_ports {adc_dat_i[0][14]}]
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set_property PACKAGE_PIN V16 [get_ports {adc_dat_i[0][15]}]
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# ADC 1 data
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set_property PACKAGE_PIN T17 [get_ports {adc_dat_i[1][0]}]
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set_property PACKAGE_PIN R16 [get_ports {adc_dat_i[1][1]}]
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set_property PACKAGE_PIN R18 [get_ports {adc_dat_i[1][2]}]
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set_property PACKAGE_PIN P16 [get_ports {adc_dat_i[1][3]}]
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set_property PACKAGE_PIN P18 [get_ports {adc_dat_i[1][4]}]
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set_property PACKAGE_PIN N17 [get_ports {adc_dat_i[1][5]}]
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set_property PACKAGE_PIN R19 [get_ports {adc_dat_i[1][6]}]
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set_property PACKAGE_PIN T20 [get_ports {adc_dat_i[1][7]}]
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set_property PACKAGE_PIN T19 [get_ports {adc_dat_i[1][8]}]
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set_property PACKAGE_PIN U20 [get_ports {adc_dat_i[1][9]}]
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set_property PACKAGE_PIN V20 [get_ports {adc_dat_i[1][10]}]
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set_property PACKAGE_PIN W20 [get_ports {adc_dat_i[1][11]}]
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set_property PACKAGE_PIN W19 [get_ports {adc_dat_i[1][12]}]
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set_property PACKAGE_PIN Y19 [get_ports {adc_dat_i[1][13]}]
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set_property PACKAGE_PIN W18 [get_ports {adc_dat_i[1][14]}]
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set_property PACKAGE_PIN Y18 [get_ports {adc_dat_i[1][15]}]
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set_property IOSTANDARD DIFF_HSTL_I_18 [get_ports adc_clk_i[*]]
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set_property PACKAGE_PIN U18 [get_ports adc_clk_i[1]]
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set_property PACKAGE_PIN U19 [get_ports adc_clk_i[0]]
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# Output ADC clock
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set_property IOSTANDARD LVCMOS18 [get_ports {adc_clk_o[*]}]
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set_property SLEW FAST [get_ports {adc_clk_o[*]}]
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set_property DRIVE 8 [get_ports {adc_clk_o[*]}]
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#set_property IOB TRUE [get_ports {adc_clk_o[*]}]
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set_property PACKAGE_PIN N20 [get_ports {adc_clk_o[0]}]
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set_property PACKAGE_PIN P20 [get_ports {adc_clk_o[1]}]
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# ADC clock stabilizer
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set_property IOSTANDARD LVCMOS18 [get_ports adc_cdcs_o]
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set_property PACKAGE_PIN V18 [get_ports adc_cdcs_o]
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set_property SLEW FAST [get_ports adc_cdcs_o]
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set_property DRIVE 8 [get_ports adc_cdcs_o]
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### DAC
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# data
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set_property IOSTANDARD LVCMOS33 [get_ports {dac_dat_o[*]}]
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set_property SLEW SLOW [get_ports {dac_dat_o[*]}]
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set_property DRIVE 4 [get_ports {dac_dat_o[*]}]
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#set_property IOB TRUE [get_ports {dac_dat_o[*]}]
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set_property PACKAGE_PIN M19 [get_ports {dac_dat_o[0]}]
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set_property PACKAGE_PIN M20 [get_ports {dac_dat_o[1]}]
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set_property PACKAGE_PIN L19 [get_ports {dac_dat_o[2]}]
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set_property PACKAGE_PIN L20 [get_ports {dac_dat_o[3]}]
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set_property PACKAGE_PIN K19 [get_ports {dac_dat_o[4]}]
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set_property PACKAGE_PIN J19 [get_ports {dac_dat_o[5]}]
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set_property PACKAGE_PIN J20 [get_ports {dac_dat_o[6]}]
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set_property PACKAGE_PIN H20 [get_ports {dac_dat_o[7]}]
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set_property PACKAGE_PIN G19 [get_ports {dac_dat_o[8]}]
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set_property PACKAGE_PIN G20 [get_ports {dac_dat_o[9]}]
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set_property PACKAGE_PIN F19 [get_ports {dac_dat_o[10]}]
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set_property PACKAGE_PIN F20 [get_ports {dac_dat_o[11]}]
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set_property PACKAGE_PIN D20 [get_ports {dac_dat_o[12]}]
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set_property PACKAGE_PIN D19 [get_ports {dac_dat_o[13]}]
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# control
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set_property IOSTANDARD LVCMOS33 [get_ports dac_*_o]
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set_property SLEW FAST [get_ports dac_*_o]
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set_property DRIVE 8 [get_ports dac_*_o]
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#set_property IOB TRUE [get_ports dac_*_o]
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set_property PACKAGE_PIN M17 [get_ports dac_wrt_o]
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set_property PACKAGE_PIN N16 [get_ports dac_sel_o]
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set_property PACKAGE_PIN M18 [get_ports dac_clk_o]
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set_property PACKAGE_PIN N15 [get_ports dac_rst_o]
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### PWM DAC
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set_property IOSTANDARD LVCMOS18 [get_ports {dac_pwm_o[*]}]
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set_property SLEW FAST [get_ports {dac_pwm_o[*]}]
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set_property DRIVE 12 [get_ports {dac_pwm_o[*]}]
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set_property IOB TRUE [get_ports {dac_pwm_o[*]}]
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set_property PACKAGE_PIN T10 [get_ports {dac_pwm_o[0]}]
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set_property PACKAGE_PIN T11 [get_ports {dac_pwm_o[1]}]
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set_property PACKAGE_PIN P15 [get_ports {dac_pwm_o[2]}]
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set_property PACKAGE_PIN U13 [get_ports {dac_pwm_o[3]}]
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#### XADC
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#set_property IOSTANDARD LVCMOS33 [get_ports {vinp_i[*]}]
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#set_property IOSTANDARD LVCMOS33 [get_ports {vinn_i[*]}]
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##AD0
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#set_property PACKAGE_PIN C20 [get_ports {vinp_i[1]}]
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#set_property PACKAGE_PIN B20 [get_ports {vinn_i[1]}]
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##AD1
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#set_property PACKAGE_PIN E17 [get_ports {vinp_i[2]}]
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#set_property PACKAGE_PIN D18 [get_ports {vinn_i[2]}]
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##AD8
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#set_property PACKAGE_PIN B19 [get_ports {vinp_i[0]}]
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#set_property PACKAGE_PIN A20 [get_ports {vinn_i[0]}]
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##AD9
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#set_property PACKAGE_PIN E18 [get_ports {vinp_i[3]}]
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#set_property PACKAGE_PIN E19 [get_ports {vinn_i[3]}]
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##V_0
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#set_property PACKAGE_PIN K9 [get_ports {vinp_i[4]}]
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#set_property PACKAGE_PIN L10 [get_ports {vinn_i[4]}]
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### Expansion connector
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set_property IOSTANDARD LVCMOS33 [get_ports {exp_p_io[*]}]
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set_property IOSTANDARD LVCMOS33 [get_ports {exp_n_io[*]}]
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set_property SLEW FAST [get_ports {exp_p_io[*]}]
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set_property SLEW FAST [get_ports {exp_n_io[*]}]
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set_property DRIVE 8 [get_ports {exp_p_io[*]}]
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set_property DRIVE 8 [get_ports {exp_n_io[*]}]
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set_property PACKAGE_PIN G17 [get_ports {exp_p_io[0]}]
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set_property PACKAGE_PIN G18 [get_ports {exp_n_io[0]}]
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set_property PACKAGE_PIN H16 [get_ports {exp_p_io[1]}]
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set_property PACKAGE_PIN H17 [get_ports {exp_n_io[1]}]
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set_property PACKAGE_PIN J18 [get_ports {exp_p_io[2]}]
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set_property PACKAGE_PIN H18 [get_ports {exp_n_io[2]}]
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set_property PACKAGE_PIN K17 [get_ports {exp_p_io[3]}]
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set_property PACKAGE_PIN K18 [get_ports {exp_n_io[3]}]
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set_property PACKAGE_PIN L14 [get_ports {exp_p_io[4]}]
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set_property PACKAGE_PIN L15 [get_ports {exp_n_io[4]}]
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set_property PACKAGE_PIN L16 [get_ports {exp_p_io[5]}]
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set_property PACKAGE_PIN L17 [get_ports {exp_n_io[5]}]
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set_property PACKAGE_PIN K16 [get_ports {exp_p_io[6]}]
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set_property PACKAGE_PIN J16 [get_ports {exp_n_io[6]}]
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set_property PACKAGE_PIN M14 [get_ports {exp_p_io[7]}]
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set_property PACKAGE_PIN M15 [get_ports {exp_n_io[7]}]
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#set_property PULLDOWN TRUE [get_ports {exp_p_io[0]}]
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#set_property PULLDOWN TRUE [get_ports {exp_n_io[0]}]
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#set_property PULLUP TRUE [get_ports {exp_p_io[7]}]
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#set_property PULLUP TRUE [get_ports {exp_n_io[7]}]
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# Pull down digital inputs.
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set_property PULLDOWN TRUE [get_ports {exp_p_io[0]}]
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set_property PULLDOWN TRUE [get_ports {exp_p_io[1]}]
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set_property PULLDOWN TRUE [get_ports {exp_p_io[2]}]
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set_property PULLDOWN TRUE [get_ports {exp_p_io[3]}]
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#### SATA connector
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#set_property IOSTANDARD LVCMOS18 [get_ports {daisy_p_o[*]}]
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#set_property IOSTANDARD LVCMOS18 [get_ports {daisy_n_o[*]}]
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#set_property IOSTANDARD LVCMOS18 [get_ports {daisy_p_i[*]}]
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#set_property IOSTANDARD LVCMOS18 [get_ports {daisy_n_i[*]}]
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#
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#set_property PACKAGE_PIN T12 [get_ports {daisy_p_o[0]}]
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#set_property PACKAGE_PIN U12 [get_ports {daisy_n_o[0]}]
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#set_property PACKAGE_PIN U14 [get_ports {daisy_p_o[1]}]
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#set_property PACKAGE_PIN U15 [get_ports {daisy_n_o[1]}]
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#set_property PACKAGE_PIN P14 [get_ports {daisy_p_i[0]}]
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#set_property PACKAGE_PIN R14 [get_ports {daisy_n_i[0]}]
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#set_property PACKAGE_PIN N18 [get_ports {daisy_p_i[1]}]
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#set_property PACKAGE_PIN P19 [get_ports {daisy_n_i[1]}]
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### LED
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set_property IOSTANDARD LVCMOS33 [get_ports {led_o[*]}]
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set_property SLEW SLOW [get_ports {led_o[*]}]
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set_property DRIVE 4 [get_ports {led_o[*]}]
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set_property PACKAGE_PIN F16 [get_ports {led_o[0]}]
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set_property PACKAGE_PIN F17 [get_ports {led_o[1]}]
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set_property PACKAGE_PIN G15 [get_ports {led_o[2]}]
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set_property PACKAGE_PIN H15 [get_ports {led_o[3]}]
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set_property PACKAGE_PIN K14 [get_ports {led_o[4]}]
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set_property PACKAGE_PIN G14 [get_ports {led_o[5]}]
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set_property PACKAGE_PIN J15 [get_ports {led_o[6]}]
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set_property PACKAGE_PIN J14 [get_ports {led_o[7]}]
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############################################################################
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# Clock constraints #
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############################################################################
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#NET "adc_clk" TNM_NET = "adc_clk";
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#TIMESPEC TS_adc_clk = PERIOD "adc_clk" 125 MHz;
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create_clock -period 8.000 -name adc_clk [get_ports adc_clk_i[1]]
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# Add clock uncertainty for robust timing.
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set_clock_uncertainty 0.2 [get_clocks adc_clk]
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# ADC data input timing.
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# The LTC2145 datasheet says CLKOUT-to-DATA = minimum 0, maximum 0.6 ns.
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# That refers to the falling edge of CLKOUT.
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# Mapped to the rising edge: minimum 4.0, maximum 4.6 ns.
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# We add 1 ns margin.
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set_input_delay -clock adc_clk -min 3.0 [get_ports {adc_dat_i[*][*]}]
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set_input_delay -clock adc_clk -max 5.6 [get_ports {adc_dat_i[*][*]}]
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set_multicycle_path 2 -from [get_ports {adc_dat_i[*][*]}]
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# Digital inputs are asynchronous and captured in IOB flipflops.
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# Declare false path to avoid warning for unconstrained path.
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set_false_path -from [get_ports {exp_p_io[*]}]
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# Delay to LEDs does not matter; just set a long max delay.
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set_max_delay -to [get_ports {led_o[*]}] 20.0
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#create_clock -period 4.000 -name rx_clk [get_ports daisy_p_i[1]]
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#set_false_path -from [get_clocks adc_clk] -to [get_clocks dac_clk_o]
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#set_false_path -from [get_clocks adc_clk] -to [get_clocks dac_clk_2x]
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#set_false_path -from [get_clocks adc_clk] -to [get_clocks dac_clk_2p]
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#set_false_path -from [get_clocks clk_fpga_0] -to [get_clocks adc_clk]
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#set_false_path -from [get_clocks clk_fpga_0] -to [get_clocks dac_clk_1x]
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#set_false_path -from [get_clocks clk_fpga_0] -to [get_clocks dac_clk_2x]
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#set_false_path -from [get_clocks clk_fpga_0] -to [get_clocks dac_clk_2p]
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#set_false_path -from [get_clocks clk_fpga_0] -to [get_clocks ser_clk]
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#set_false_path -from [get_clocks clk_fpga_0] -to [get_clocks pdm_clk]
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#set_false_path -from [get_clocks dac_clk_o] -to [get_clocks dac_clk_2x]
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#set_false_path -from [get_clocks dac_clk_o] -to [get_clocks dac_clk_2p]
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############################################################################
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# Bit file settings #
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############################################################################
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set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
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