Joris van Rantwijk 4d79fecfdc Change FCLK0 frequency to 200 MHz ... This clock is used as REFCLK for IODELAYCTRL in the 4-input design.		2024-10-06 12:58:11 +02:00
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redpitaya_puzzlefw.srcs/sources_1/bd/puzzlefw	Change FCLK0 frequency to 200 MHz	2024-10-06 12:58:11 +02:00
nonproject.tcl	Generate FPGA datasheet report	2024-10-04 23:03:16 +02:00
redpitaya_puzzlefw.xpr	Add timetagger logic to Vivado project	2024-09-21 20:20:36 +02:00