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joris
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redpitaya-puzzlefw
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redpitaya-puzzlefw
/
fpga
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Joris van Rantwijk
8562c9346d
Remove digital debug output signals
2024-08-31 13:17:22 +02:00
..
constraints
Set PULLDOWN on digital inputs
2024-08-29 10:03:00 +02:00
rtl
Remove digital debug output signals
2024-08-31 13:17:22 +02:00
vivado
Add timetagger logic
2024-08-30 23:04:02 +02:00
.gitignore
Ignore Vivado output files
2024-08-29 12:37:56 +02:00
01_get_redpitaya.sh
Update block design and Vivado project
2024-08-27 22:40:01 +02:00
11_build_bitfile.sh
Log synthesizer messages to file
2024-08-30 23:04:27 +02:00
script_env
Script to build bitfile
2024-08-03 13:14:19 +02:00