redpitaya-puzzlefw/fpga
Joris van Rantwijk 5d00a2e792 Read digital input signals 2024-08-27 23:48:12 +02:00
..
constraints Add Vivado project 2024-08-03 12:55:15 +02:00
rtl Read digital input signals 2024-08-27 23:48:12 +02:00
vivado Read digital input signals 2024-08-27 23:48:12 +02:00
.gitignore gitignore Vivado generated files 2024-08-03 13:14:17 +02:00
01_get_redpitaya.sh Update block design and Vivado project 2024-08-27 22:40:01 +02:00
11_build_bitfile.sh Update block design and Vivado project 2024-08-27 22:40:01 +02:00
script_env Script to build bitfile 2024-08-03 13:14:19 +02:00