Joris van Rantwijk 5632ffc6b2 Add VHDL for DMA write channel		2024-08-09 20:16:53 +02:00
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redpitaya_puzzlefw.srcs/sources_1/bd/puzzlefw	Disable Hierarchical synthesis of block design	2024-08-03 12:55:22 +02:00
nonproject.tcl	Add VHDL for DMA write channel	2024-08-09 20:16:53 +02:00
redpitaya_puzzlefw.xpr	Add Vivado project	2024-08-03 12:55:15 +02:00