constraints
|
Add Vivado project
|
2024-08-03 12:55:15 +02:00 |
rtl
|
Rework DMA to support single-beat transfers
|
2024-08-24 23:04:35 +02:00 |
vivado
|
Add VHDL for DMA write channel
|
2024-08-09 20:16:53 +02:00 |
.gitignore
|
gitignore Vivado generated files
|
2024-08-03 13:14:17 +02:00 |
01_build_bitfile.sh
|
Script to build bitfile
|
2024-08-03 13:14:19 +02:00 |
script_env
|
Script to build bitfile
|
2024-08-03 13:14:19 +02:00 |