redpitaya-puzzlefw/fpga
Joris van Rantwijk 38281d814d Separate register for acquisition DMA channel status 2024-08-27 16:03:31 +02:00
..
constraints Add Vivado project 2024-08-03 12:55:15 +02:00
rtl Separate register for acquisition DMA channel status 2024-08-27 16:03:31 +02:00
vivado Add monitoring of ADC sample and min/max range 2024-08-26 23:11:16 +02:00
.gitignore gitignore Vivado generated files 2024-08-03 13:14:17 +02:00
01_build_bitfile.sh Script to build bitfile 2024-08-03 13:14:19 +02:00
script_env Script to build bitfile 2024-08-03 13:14:19 +02:00