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redpitaya-puzzlefw
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redpitaya-puzzlefw/fpga/vivado
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Joris van Rantwijk 33db3d5231 Remove board name from FPGA build script 2024-10-08 16:48:11 +02:00
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redpitaya_puzzlefw.srcs/sources_1/bd/puzzlefw Change FCLK0 frequency to 200 MHz 2024-10-06 12:58:11 +02:00
nonproject.tcl Remove board name from FPGA build script 2024-10-08 16:48:11 +02:00
redpitaya_puzzlefw.xpr Add timetagger logic to Vivado project 2024-09-21 20:20:36 +02:00