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joris
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redpitaya-puzzlefw
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1cbe2cc0c9
redpitaya-puzzlefw
/
fpga
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Joris van Rantwijk
1cbe2cc0c9
Set PULLDOWN on digital inputs
2024-08-29 10:03:00 +02:00
..
constraints
Set PULLDOWN on digital inputs
2024-08-29 10:03:00 +02:00
rtl
Drive unused output ports
2024-08-29 10:01:55 +02:00
vivado
Read digital input signals
2024-08-27 23:48:12 +02:00
.gitignore
gitignore Vivado generated files
2024-08-03 13:14:17 +02:00
01_get_redpitaya.sh
Update block design and Vivado project
2024-08-27 22:40:01 +02:00
11_build_bitfile.sh
Update block design and Vivado project
2024-08-27 22:40:01 +02:00
script_env
Script to build bitfile
2024-08-03 13:14:19 +02:00