402 lines
14 KiB
VHDL
402 lines
14 KiB
VHDL
--
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-- Management of DMA transfers from FPGA to memory.
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--
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-- Joris van Rantwijk 2024
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--
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use work.puzzlefw_pkg.all;
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entity dma_write_channel is
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generic (
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-- Preferred DMA burst length as the 2-log of the number of beats.
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-- Transactions will use the preferred burst length unless there
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-- are fewer words available in the buffer.
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transfer_size_bits: integer range 0 to 4 := 4;
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-- Size of the input data queue as 2-log of the number of words.
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queue_size_bits: integer range 5 to 16 := 10;
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-- Number of clock cycles to wait before starting a small DMA burst.
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idle_timeout: natural := 256
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);
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port (
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-- Main clock, active on rising edge.
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clk: in std_logic;
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-- Reset, active high, synchronous to main clock.
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reset: in std_logic;
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-- High to enable the channel, low to pause the channel.
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-- When channel_en is low, any ongoing transfer will be completed but
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-- no new transfer will be started.
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channel_en: in std_logic;
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-- High if there uncompleted DMA transfers are in progress.
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-- If a DMA error occurs, the channel may get stuck in a busy state.
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channel_busy: out std_logic;
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-- High to initialize the channel.
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--
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-- This resets the write pointer to the start of the buffer and deletes
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-- all data from the queue.
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--
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-- This function must be used whenever the buffer address range is changed.
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-- This function must not be used while uncompleted DMA transfers
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-- are in progress, except to recover from an error.
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channel_init: in std_logic;
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-- Start and end address of the DMA buffer.
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-- Both addresses are relative to the DMA window base address.
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-- The write pointer wraps to the start address when it would
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-- have reached the end address.
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addr_start: in std_logic_vector(31 downto 7);
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addr_end: in std_logic_vector(31 downto 7);
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-- When the write pointer reaches the limit address, DMA transfers
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-- are paused until software updates the limit.
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addr_limit: in std_logic_vector(31 downto 7);
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-- An interrupt is triggered when the write pointer equals the
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-- interrupt address.
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addr_interrupt: in std_logic_vector(31 downto 3);
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-- Write pointer.
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addr_pointer: out std_logic_vector(31 downto 3);
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-- High to enable interrupt on reaching a configured address.
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intr_en: in std_logic;
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-- Pulsed high to clear a previous interrupt condition.
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intr_clear: in std_logic;
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-- High if an enabled interrupt condition occurred and the interrupt
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-- has not been cleared yet.
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intr_out: out std_logic;
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-- Input data stream to the channel.
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in_valid: in std_logic;
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in_ready: out std_logic;
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in_data: in dma_data_type;
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-- Signals to AXI master.
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write_cmd_addr: out dma_address_type;
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write_cmd_length: out dma_burst_length_type;
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write_cmd_valid: out std_logic;
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write_cmd_ready: in std_logic;
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write_data: out dma_data_type;
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write_data_ready: in std_logic;
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write_finished: in std_logic
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);
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end entity;
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architecture arch of dma_write_channel is
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constant transfer_size: integer range 1 to 16 := 2**transfer_size_bits;
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type state_type is (STATE_SINGLE_IDLE, STATE_SINGLE_START, STATE_SINGLE_DATA,
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STATE_BURST_PREPARE,
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STATE_BURST_IDLE, STATE_BURST_START, STATE_BURST_DATA);
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type regs_type is record
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cmd_valid: std_logic;
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cmd_addr: std_logic_vector(31 downto 3);
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cmd_full_burst: std_logic;
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addr_pointer: std_logic_vector(31 downto 3);
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intr_out: std_logic;
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channel_busy: std_logic;
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state: state_type;
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pending_beats: unsigned(3 downto 0);
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pending_transfers: unsigned(3 downto 0);
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idle_timer: integer range 0 to idle_timeout - 1;
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end record;
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constant regs_init: regs_type := (
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cmd_valid => '0',
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cmd_addr => (others => '0'),
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cmd_full_burst => '0',
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addr_pointer => (others => '0'),
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intr_out => '0',
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channel_busy => '0',
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state => STATE_SINGLE_IDLE,
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pending_beats => (others => '0'),
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pending_transfers => (others => '0'),
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idle_timer => 0
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);
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signal r: regs_type := regs_init;
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signal rnext: regs_type;
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signal s_fifo_reset: std_logic;
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signal s_fifo_valid: std_logic;
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signal s_fifo_length: unsigned(queue_size_bits - 1 downto 0);
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-- Return true if address is aligned to a full-size burst.
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function is_address_aligned(addr: std_logic_vector(31 downto 3))
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return boolean
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is begin
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if transfer_size = 1 then
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return true;
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else
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return (unsigned(addr(transfer_size_bits + 2 downto 3)) = 0);
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end if;
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end function;
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begin
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--
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-- Data FIFO.
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--
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inst_fifo: entity work.simple_fifo
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generic map (
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data_width => 64,
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fifo_depth_bits => queue_size_bits )
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port map (
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clk => clk,
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reset => s_fifo_reset,
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in_valid => in_valid,
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in_ready => in_ready,
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in_data => in_data,
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out_valid => s_fifo_valid,
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out_ready => write_data_ready,
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out_data => write_data,
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queue_length => s_fifo_length );
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-- Drive output ports.
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channel_busy <= r.channel_busy;
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addr_pointer <= r.addr_pointer;
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intr_out <= r.intr_out;
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write_cmd_addr <= r.cmd_addr;
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write_cmd_length <= "0000" when (r.cmd_full_burst = '0') else
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std_logic_vector(to_unsigned(transfer_size - 1, 4));
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write_cmd_valid <= r.cmd_valid;
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-- Drive reset signal to FIFO.
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s_fifo_reset <= reset or channel_init;
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--
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-- Combinatorial process.
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--
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process (all) is
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variable v: regs_type;
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begin
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-- Load current register values.
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v := r;
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-- State machine.
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case r.state is
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when STATE_SINGLE_IDLE =>
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v.cmd_full_burst := '0';
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-- Clear busy flag.
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if r.pending_transfers = 0 then
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v.channel_busy := '0';
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end if;
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-- Update idle timer.
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if (s_fifo_valid = '1') and (r.idle_timer /= idle_timeout - 1) then
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v.idle_timer := r.idle_timer + 1;
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end if;
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-- Switch to burst mode if the FIFO has enough data,
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-- and the address is aligned to a full burst.
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if (transfer_size > 1)
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and (s_fifo_length >= transfer_size)
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and is_address_aligned(r.cmd_addr) then
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v.state := STATE_BURST_PREPARE;
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-- Otherwise, start a single-beat transfer when possible.
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elsif (channel_en = '1')
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and (s_fifo_valid = '1')
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and (r.cmd_addr(31 downto 7) /= addr_limit)
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and (r.pending_transfers /= 15)
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and ((transfer_size = 1)
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or (not is_address_aligned(r.cmd_addr))
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or (r.idle_timer = idle_timeout - 1)) then
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v.cmd_valid := '1';
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v.channel_busy := '1';
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v.pending_beats := to_unsigned(0, v.pending_beats'length);
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v.state := STATE_SINGLE_START;
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end if;
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when STATE_SINGLE_START =>
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-- Wait until start of transfer.
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if write_cmd_ready = '1' then
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v.cmd_valid := '0';
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-- Update pending transfers.
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v.pending_transfers := r.pending_transfers + 1;
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-- Update command address.
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v.cmd_addr := std_logic_vector(unsigned(r.cmd_addr) + 1);
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if v.cmd_addr(31 downto 7) = addr_end then
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-- Wrap at end of buffer.
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v.cmd_addr := addr_start & "0000";
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end if;
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if write_data_ready = '1' then
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v.state := STATE_SINGLE_IDLE;
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else
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v.state := STATE_SINGLE_DATA;
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end if;
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end if;
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-- Reset idle counter.
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v.idle_timer := 0;
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when STATE_SINGLE_DATA =>
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-- Wait until data accepted.
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if (write_data_ready = '1') and (r.pending_beats = 0) then
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v.state := STATE_SINGLE_IDLE;
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end if;
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when STATE_BURST_PREPARE =>
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-- Wait until pending transfers are completed.
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if r.pending_transfers = 0 then
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v.state := STATE_BURST_IDLE;
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end if;
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-- Reset idle counter.
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v.idle_timer := 0;
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when STATE_BURST_IDLE =>
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v.cmd_full_burst := '1';
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-- Clear busy flag.
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if r.pending_transfers = 0 then
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v.channel_busy := '0';
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end if;
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-- Switch to single transfer mode if FIFO has insufficient data.
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if (s_fifo_length < transfer_size)
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and (r.pending_transfers = 0) then
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v.state := STATE_SINGLE_IDLE;
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end if;
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-- Start a burst transfer if possible.
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if (channel_en = '1')
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and (s_fifo_length >= transfer_size)
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and (r.cmd_addr(31 downto 7) /= addr_limit)
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and (r.pending_transfers /= 15) then
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v.cmd_valid := '1';
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v.channel_busy := '1';
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v.pending_beats := to_unsigned(transfer_size - 1, v.pending_beats'length);
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v.state := STATE_BURST_START;
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end if;
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when STATE_BURST_START =>
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-- Wait until start of transfer.
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if write_cmd_ready = '1' then
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v.cmd_valid := '0';
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-- Update pending transfers.
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v.pending_transfers := r.pending_transfers + 1;
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-- Update command address.
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v.cmd_addr := std_logic_vector(unsigned(r.cmd_addr) + transfer_size);
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if v.cmd_addr(31 downto 7) = addr_end then
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-- Wrap at end of buffer.
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v.cmd_addr := addr_start & "0000";
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end if;
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v.state := STATE_BURST_DATA;
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end if;
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when STATE_BURST_DATA =>
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-- Wait until last beat.
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if (write_data_ready = '1') and (r.pending_beats = 0) then
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v.state := STATE_BURST_IDLE;
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end if;
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end case;
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-- Count write beats to find end of transfer.
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if write_data_ready = '1' then
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v.pending_beats := r.pending_beats - 1;
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end if;
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-- Update pointer on write completion.
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if (write_finished = '1') and (r.pending_transfers /= 0) then
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v.pending_transfers := v.pending_transfers - 1;
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if r.cmd_full_burst = '1' then
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-- Completion of a full burst.
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v.addr_pointer := std_logic_vector(unsigned(r.addr_pointer) + transfer_size);
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-- Raise interrupt when pointer passes threshold.
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if (intr_en = '1')
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and (r.addr_pointer(31 downto 3 + transfer_size_bits)
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= addr_interrupt(31 downto 3 + transfer_size_bits)) then
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v.intr_out := '1';
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end if;
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else
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-- Completion of single transfer.
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v.addr_pointer := std_logic_vector(unsigned(r.addr_pointer) + 1);
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end if;
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-- Wrap at end of buffer.
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if v.addr_pointer(31 downto 7) = addr_end then
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v.addr_pointer := addr_start & "0000";
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end if;
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end if;
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-- Raise interrupt when pointer equals threshold.
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if (intr_en = '1') and (r.addr_pointer = addr_interrupt) then
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v.intr_out := '1';
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end if;
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-- Clear interrupt.
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if intr_clear = '1' then
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v.intr_out := '0';
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end if;
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-- Initialize pointers.
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if channel_init = '1' then
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v.cmd_addr := addr_start & "0000";
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v.addr_pointer := addr_start & "0000";
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v.state := STATE_SINGLE_IDLE;
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v.pending_transfers := (others => '0');
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v.idle_timer := 0;
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end if;
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-- Synchronous reset.
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if reset = '1' then
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v := regs_init;
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end if;
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-- Drive new register values to synchronous process.
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rnext <= v;
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end process;
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--
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-- Synchronous process.
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--
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process (clk) is
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begin
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if rising_edge(clk) then
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r <= rnext;
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end if;
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end process;
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end architecture;
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