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redpitaya-puzzlefw
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redpitaya-puzzlefw/fpga/rtl
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Joris van Rantwijk 4abc2ee165 Rework DMA to support single-beat transfers 2024-08-24 23:04:35 +02:00
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dma_axi_master.vhd Rework DMA to support single-beat transfers 2024-08-24 23:04:35 +02:00
dma_write_channel.vhd Rework DMA to support single-beat transfers 2024-08-24 23:04:35 +02:00
puzzlefw_pkg.vhd Rework DMA to support single-beat transfers 2024-08-24 23:04:35 +02:00
puzzlefw_top.vhd Rework DMA to support single-beat transfers 2024-08-24 23:04:35 +02:00
registers.vhd Rework DMA to support single-beat transfers 2024-08-24 23:04:35 +02:00
simple_fifo.vhd Add VHDL for DMA write channel 2024-08-09 20:16:53 +02:00