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---
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gitea: none
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include_toc: true
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---
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# PuzzleFW User Manual
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PuzzleFW is an alternative, unofficial firmware package for the Red Pitaya.
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It consists of FPGA firmware and embedded software.
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The embedded software runs under Linux on the ARM processor in the Zynq.
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The PuzzleFW firmware does not provide a built-in user interface.
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It does not have a web interface, nor any other kind of graphical interface.
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The only way to control the system is via the network, using a remote command protocol.
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In typical cases, you would design custom PC software that connects to the Red Pitaya via the network to send commands and receive data.
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Such software can then present the measured data on the PC in any way it wants, possibly via a custom graphical user interface.
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## Analog input operation
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The analog input subsystem captures ADC samples.
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Depending on various configuration settings, the ADC samples are processed and ultimately transferred via the network.
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### Analog input signals
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A standard Red Pitaya STEMlab 125-14 has 2 analog input channels,
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sampled by one dual-input ADC.
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The analog inputs are labeled as channel 1 and channel 2.
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A Red Pitaya STEMlab 125-14 4-input has 4 analog input channels,
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sampled by a pair of dual-input ADCs.
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The analog inputs are labeled as channel 1 to channel 4.
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On a 4-input system, the firmware can operate either in 2-channel mode or
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in 4-channel mode.
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In 2-channel mode, only samples from channel 1 and channel 2 are processed.
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### Sampling
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All analog input channels are simultaneously sampled at a fixed
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sample rate of 125 MSa/s.
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Samples are unsigned 14-bit integers.
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An input level of 0 Volt corresponds to the middle of the 14-bit range,
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i.e. approximately 8192.
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Since the Red Pitaya uses an inverting input circuit.
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positive input voltages correspond to lower ADC codes,
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and negative input voltages correspond to higher ADC codes.
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### Downsampling (decimation)
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The ADCs operate at a fixed sample rate of 125 MSa/s.
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While the sample rate of the ADC can not be changed, the effective sample rate can be reduced by digital processing in the FPGA.
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The effective sample rate after digital processing is equal to the ADC sample rate divided by the _sample rate divisor_ (also called _downsample factor_ or _decimation factor_).
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The sample rate divisor is always an integer.
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Setting the sample rate divisor to 1 results in an effective sample rate equal to the ADC sample rate, i.e. 125 MSa/s.
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Setting a higher sample rate divisor reduces the effective sample rate to `125000000 / divisor` samples per second.
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The maximum supported sample rate divisor is 2<sup>18</sup>, corresponding to
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an effective sample rate of approximately 477 samples/s.
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Rather than configuring the sample rate divisor, the system also supports configuring an effective sample rate in samples per second.
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In this case, the requested sample rate is converted to the corresponding sample rate divisor and rounded to the nearest integer.
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The system supports two modes of sample rate reduction: decimation and averaging.
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In decimation mode with sample rate divisor _N_, only the first sample out of every group of _N_ samples is processed, and the remaining _N_ - 1 samples are discarded.
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Decimation causes high frequency signals (above the Nyquist frequency) to alias into the downsampled data.
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In averaging mode, the system calculates the sum of each group of _N_ samples.
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Averaging mode has the advantage that it suppresses aliasing and noise.
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For this reason, averaging mode is the default setting.
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Averaging mode is implemented by summing sample values.
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This causes an effective gain factor that depends on the sample rate divisor:
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if _N_ samples are summed, the result is equal to _N_ times the average
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sample value.
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If the sample rate divisor is greater than 1024, the result may not fit
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in a 24-bit word.
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To fix this, the summed values are divided by a suitable power of 2. <br>
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If _N_ ≤ 1024, the effective downsample gain is equal to _N_. <br>
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If _N_ > 1024, the effective downsample gain is equal to _N_ / 2<sup>_k_</sup>, where _k_ = ceil(log<sub>2</sub>(_N_ / 1024)).
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### Triggering
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When a trigger occurs, the system collects a record consisting of a
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configurable number of (downsampled) samples.
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Samples are collected for all active channels.
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The number of samples collected per trigger must be between 1 and 65536.
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Collected samples are transferred via the network.
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There are 3 ways to trigger the system:
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- By sending an explicit trigger command.
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- Via an external digital input signal.
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A record is collected for each trigger pulse in the digital signal.
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- Continuous triggering in auto-trigger mode.
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There are 4 digital input signals that can be used for external triggering.
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These signals are connected via pins `DIO0_P` to `DIO3_P` on the Red Pitaya.
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Settings are available to select one of these signals, and
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to trigger on either rising or falling edges of the selected signal.
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An optional trigger delay can be specified.
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The delay specifies the number of 8 ns cycles to wait after detecting
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the trigger event and before recording the first ADC sample.
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The external trigger event is subject to a jitter of 1 sample (8 ns).
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New trigger events are ignored while the system is still processing a previous trigger.
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When auto-trigger mode is active, the system triggers continuously.
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A new trigger occurs as soon as acquisition for the previous trigger has ended, after a dead time controlled by the trigger delay setting.
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In this mode, the sample rate divisor must be at least 2 (or at least 4 in 4-channel mode).
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If the trigger delay is zero, sampling continues accross triggers at a fixed pace controlled by the sample rate divisor.
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This makes it possible to set up continuous streaming sampling.
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### Performance limits
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Sample rates are limited in a number of ways:
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- For acquisition runs up to about 16000 samples, the sample rate
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is limited by internal data paths in the FPGA.
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In this case, the sample rate divisor must be at least 1,
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or at least 2 when operating in 4-channel mode.
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- However, in auto-trigger mode, even for short acquisition runs,
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the sample rate divisor must be at least 2,
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or at least 4 when operating in 4-channel mode.
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- For longer acquisition runs, the sample rate is limited by the
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network transfer rate.
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In this case, the maximum sample rate is approximately 5 MSa/s,
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or 2.5 MSa/s when operating in 4-channel mode.
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If the configured sample rate is too high, the system will either
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refuse the sample rate setting, or sample data will be lost
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when internal data buffers fill up.
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When using external triggering, the maximum trigger rate depends
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on the time it takes to complete data collection for a trigger.
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The system is ready to accept a new trigger as soon as data collection
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for the previous trigger ends.
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At high sample rates, the maximum trigger rate is eventually also limited
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by the data transfer rate via the network.
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### Calibration
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The analog inputs of the Red Pitaya support two different input ranges:
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± 1 V and ± 20 V.
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The range is selected through jumpers on the board.
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Software commands can not change the actual input range.
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The firmware does provide commands to specify which input range is used by each channel.
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The firmware also keeps track of calibration coefficients for each channel
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and input range.
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Two calibration coefficients, _offset_ and _gain_, establish a linear relation
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between ADC codes and input voltage.
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The conversion formula is as follows:
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adc_code = offset + gain * input_voltage
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Input ranges and calibration coefficients can be saved to the SD card of
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the Red Pitaya to be preserved across power cycles.
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## Timetagger operation
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The timetagger subsystem detects changes on digital input signals
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and assigns timestamps to such events.
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The stream of timetagged events is transferred via the network.
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The timestamp resolution is the same as the ADC sample rate, 125 MHz.
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Timestamps are expressed in units of 8 ns cycles.
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### Digital input signals
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The timetagger has 4 digital input channels.
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These signals are connected via pins `DIO0_P` to `DIO3_P` on the Red Pitaya.
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Each input channel produces two types of events: rising edge events and falling edge events.
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Each event type of each channel can be separately enabled or disabled for timetagging.
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## Firmware installation
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- Use a micro SD card, at least 1 GB.
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- Get the PuzzleFW firmware image `puzzlefw_sdcard.img`
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- Put the SD card in a Linux PC.
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- Find out the device name of the SD card `/dev/sdX` where `X` is replaced by another letter.
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Be **very careful** to get the device name right.
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Other storage devices in the PC have similar names.
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Writing the image will destroy all other data on the target device.
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If you accidentally write the image to the main drive of your PC, you will have a very bad day.
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- Make sure that the SD card is not mounted by some automatic device management subsystem in your PC.
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- Run the following command as root: <br>
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`dd if=puzzlefw_sdcard.img of=/dev/sdX bs=1M`
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<br>
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This command may take a few minutes to complete.
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- Run `sync` and `eject /dev/sdX` before removing the SD card from the PC.
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The SD card image can also be written on a PC with a different operating system than Linux.
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The steps to do this are described in the official Red Pitaya documentation.
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## Console access
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The USB console port on the Red Pitaya can be used to login on
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the Linux system running on the board.
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This is mostly useful for debugging.
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To access the console, use a terminal program such as `minicom`
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to open the USB serial port of the Red Pitaya.
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Set the baud rate to 115200 bps, character format to `8N1`.
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Press Enter to get a login prompt on the console.
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Use login `root` with password `root`.
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## Network access
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Remote access to the acquisition system is supported via TCP connections.
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Three TCP server ports are used:
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- port 5001 is used to transfer analog sample data;
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- port 5002 is used to transfer timetagger data;
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- port 5025 is used for commands.
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### Default IP address settings
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By default, the system attempts to obtain an IPv4 address via DHCP.
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If the DHCP request fails, the system chooses a link-local address in
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the range 169.254.x.x.
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As an alternative to DHCP, a static IPv4 address can be configured via remote control commands.
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The system has a unique host name `rp-xxxxxx.local`,
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where the x characters are replaced by the last 6 digits of
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the MAC address.
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This is the same host name as used by the official Red Pitaya software.
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### SSH access
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It is possible to run an SSH server on the Red Pitaya.
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This can be used to remotely log in on the Linux system.
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To login via SSH, use username `root` with password `root`.
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For security reasons, the SSH server is disabled by default.
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An SSH server with an easy-to-guess password should never be connected to an untrusted network.
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If you want to use the SSH server, you have to enable it explicitly.
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To enable the SSH server, login on the USB console as described above.
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Then run the following command: `puzzle-sshcfg enable` .
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Finally, run `reboot` to reboot the Red Pitaya.
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From this point onward, the SSH server will be started automatically during boot.
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## Data stream protocol
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Clients may connect to TCP port 5001 to receive analog sample data,
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and to TCP port 5002 to receive timetagger data.
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At most one client can be connected to each of these ports at any time.
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If a new client connects while another connection is still active,
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the server closes the old connection and uses the new connection instead.
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Data flows through these TCP connections in one direction:
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from the server to the client.
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The client must not send anything back to the server.
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Data are transferred as a sequence of 64-bit binary messages.
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Each message is sent as 8 bytes with the least significant byte first.a
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The message streams correspond to the output data format of the
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analog acquisition chain and the timetagger as described in the
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[FPGA firmware documentation](fpga_firmware.md#).
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## Remote control protocol
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Clients may connect to TCP port 5025 to send commands.
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Multiple clients may be simultaneously connected to this port.
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In that case, it is the responsibility of the clients to make sure
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that they do not interfere with eachother.
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The remote control protocol is based on ASCII strings.
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The protocol is vaguely similar to SCPI, but it is not compatible with SCPI.
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Every interaction is initiated by the client sending a command,
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and completed by the server sending a response.
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Each command and each response consists of an ASCII string terminated by linefeed (ASCII 10).
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Commands are case-insensitive.
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The server ignores empty lines and lines that contain only white space characters.
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In all other cases, the server sends one response for every command received, even if the command is not recognized or not supported.
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The server only sends data in response to a command; it never sends data spontaneously.
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A _query_ is a command that ends with a `?` character.
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The server responds to a query either by sending the requested data,
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or by sending an error message.
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An error message starts with the string `ERROR`, followed by
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a space character, followed by a short description of the error.
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The server responds to a non-query command either by sending the string `OK`
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to indicate that the command was completed successfully,
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or by sending an error message.
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Some commands require one or more _parameters_.
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In the command string, the command and parameters are separated from eachother by space characters.
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The response to some queries may consist of multiple data elements.
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In the response string, such data elements are separated by space characters.
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### Example
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| Client | Server |
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|--------------------------|---------------|
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| `AIN:SRATE?` | |
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| | `1000000.000` |
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|
| `AIN:SRATE:DIVISOR 1000` | |
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|
|
|
|
| | `OK` |
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|
| `AIN:SRATE?` | |
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|
|
| | `125000.000` |
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| `AIN:NSAMPLES 0` | |
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|
|
|
|
| | `ERROR Invalid argument` |
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|
|
| `Hello` | |
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|
|
|
| | `ERROR Unknown command` |
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|
|
|
|
### List of commands and queries
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|
|
| Command | Description |
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|
|---------------------------|-------------|
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| `*IDN?` | Instrument identification. |
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| `RESET` | Restore default settings. |
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| `TIMESTAMP?` | Timestamp counter. |
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| `AIN:CHANNELS:COUNT?` | Number of input channels. |
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| `AIN:CHANNELS:ACTIVE` | Number of active input channels. |
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| `AIN:CHn:RANGE` | Analog input range. |
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| `AIN:CHn:OFFSET` | Offset calibration. |
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| `AIN:CHn:GAIN` | Gain calibration. |
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| `AIN:CAL:SAVE` | Save calibration. |
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| `AIN:CHn:SAMPLE[:RAW]?` | Read ADC sample. |
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| `AIN:CHn:MINMAX[:RAW]?` | Read ADC range monitor. |
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| `AIN:MINMAX:CLEAR` | Reset ADC range monitor. |
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| `AIN:SRATE` | Sample rate. |
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| `AIN:SRATE:DIVISOR` | Downsample factor. |
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| `AIN:SRATE:MODE` | Downsample mode. |
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| `AIN:SRATE:GAIN?` | Downsample gain. |
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| `AIN:NSAMPLES` | Number of samples per trigger. |
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| `AIN:TRIGGER` | Force a trigger event. |
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| `AIN:TRIGGER:MODE` | Select trigger mode. |
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| `AIN:TRIGGER:DELAY` | Trigger delay. |
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| `AIN:TRIGGER:STATUS?` | Trigger status. |
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| `AIN:TRIGGER:EXT:CHANNEL` | External trigger channel. |
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| `AIN:TRIGGER:EXT:EDGE` | External trigger edge. |
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| `AIN:ACQUIRE:ENABLE` | Enable analog acquisition. |
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| `TT:SAMPLE?` | Digital input state. |
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| `TT:EVENT:MASK` | Timetagger event mask. |
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| `TT:MARK` | Emit timetagger marker. |
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| `TEMP:FPGA?` | FPGA temperature. |
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| `IPCFG[:SAVED]` | IP address configuration. |
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| `HALT` | Shut down system. |
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| `REBOOT` | Reboot system. |
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|
|
### `*IDN?`
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Query: `*IDN?` <br>
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Response: string with 4 comma-separated fields.
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|
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This query returns the instrument identification string.
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|
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The response consists of 4 comma-separated fields:
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|
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`manufacturer,model,serialnr,version`.
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|
### `RESET`
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Command: `RESET`
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|
This command restores most non-persistent settings to power-on defaults.
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It resets all settings, except for the following:
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- saved calibration;
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|
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- active network configuration;
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|
|
- saved network configuration.
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The active calibration is restored to match the saved calibration.
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Other settings are restored to fixed power-on defaults.
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Any ongoing analog acquisition is stopped.
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|
### `TIMESTAMP?`
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Query: `TIMESTAMP?` <br>
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Response: decimal integer, representing the current timestamp in units of 8 ns.
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|
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### `AIN:CHANNELS:COUNT?`
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Query: `AIN:CHANNELS:COUNT?` <br>
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Response: number of supported analog input channels.
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|
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The response is `2` for a standard Red Pitaya, or `4` for a 4-input Red Pitaya.
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### `AIN:CHANNELS:ACTIVE`
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Command: `AIN:CHANNELS:ACTIVE n` <br>
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Parameter _n_: number of active channels, either `2` or `4`.
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This command is only supported on a 4-input Red Pitaya.
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|
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When 2 channels are active, only analog input channels 1 and 2 are included in analog acquisition data.
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|
|
Query: `AIN:CHANNELS:ACTIVE?` <br>
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|
|
Response: number of active channels, either `2` or `4`.
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|
|
### `AIN:CHn:RANGE`
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|
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Command: `AIN:CHn:RANGE range` <br>
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|
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Field _n_: channel number, in range 1 to 4. <br>
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|
|
Parameter _range_: input range, either `LO` or `HI`.
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|
|
This command specifies which set of calibration coefficients should be used to interpret ADC samples.
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|
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Note that this command does not change the actual input range of the Red Pitaya.
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|
|
The input range can only be changed by manually placing a jumper on the board.
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|
|
Query: `AIN:CHn:RANGE?` <br>
|
|
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|
|
Response: currently configured input range, either `LO` or `HI`.
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|
|
### `AIN:CHn:OFFSET[:LO|HI]`
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|
|
Command: `AIN:CHn:OFFSET offs` <br>
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|
|
Field _n_: channel number, in range 1 to 4. <br>
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|
|
Parameter _offs_: floating point number specifying the offset calibration.
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|
|
The offset calibration specifies the raw ADC code corresponding to analog input level 0 Volt.
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|
|
The expected value is in the middle of the ADC code range, i.e. approximately 8192.
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|
|
The plain variant of the command configures the offset calibration for the active input range of the channel.
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|
|
Command: `AIN:CHn:OFFSET:LO offs` <br>
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|
|
Command: `AIN:CHn:OFFSET:HI offs` <br>
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|
|
These variants of the command configure the offset calibration for a specific input range.
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|
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|
|
Query: `AIN:CHn:OFFSET?` <br>
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|
|
Query: `AIN:CHn:OFFSET:LO?` <br>
|
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|
|
Query: `AIN:CHn:OFFSET:HI?` <br>
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|
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|
|
Response: floating point number indicating the offset calibration for the active input range or the specified input range.
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|
|
### `AIN:CHn:GAIN[:LO|HI]`
|
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|
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|
|
Command: `AIN:CHn:GAIN gain` <br>
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|
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|
|
Field _n_: channel number, in range 1 to 4. <br>
|
|
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|
|
Parameter _gain_: floating point number specifying the gain calibration.
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|
|
The gain calibration specifies the difference in raw ADC code corresponding to a 1 Volt difference in analog input level.
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|
|
The expected value is negative, because the Red Pitaya uses an inverting input amplifier.
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|
|
The plain variant of the command configures the gain calibration for the active input range of the channel.
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|
|
Command: `AIN:CHn:GAIN:LO offs` <br>
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|
|
Command: `AIN:CHn:GAIN:HI offs` <br>
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|
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|
|
These variants of the command configure the gain calibration for a specific input range.
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|
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|
|
|
|
|
|
|
Query: `AIN:CHn:GAIN?` <br>
|
|
|
|
|
Query: `AIN:CHn:GAIN:LO?` <br>
|
|
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|
|
Query: `AIN:CHn:GAIN:HI?` <br>
|
|
|
|
|
Response: floating point number indicating the gain calibration for the active input range or the specified input range.
|
|
|
|
|
|
|
|
|
|
### `AIN:CAL:SAVE`
|
|
|
|
|
|
|
|
|
|
Command: `AIN:CAL:SAVE`
|
|
|
|
|
|
|
|
|
|
This command saves the active calibration settings to the SD card, to be used as power-on defaults.
|
|
|
|
|
The following settings are saved for each analog input channel: its input range, offset calibration for low and high range, and gain calibration for low and high range.
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|
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|
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|
|
### `AIN:CHn:SAMPLE[:RAW]?`
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|
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|
|
Query: `AIN:CHn:SAMPLE?` <br>
|
|
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|
|
Field _n_: channel number, in range 1 to 4. <br>
|
|
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|
|
Response: floating point number representing the most recent ADC sample for the specified input channel in Volt.
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|
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|
|
Query: `AIN:CHn:SAMPLE:RAW?` <br>
|
|
|
|
|
Response: decimal integer representing the raw ADC code of the most recent sample for the specified input channel.
|
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|
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|
|
Sample rate settings are not applicable to this command.
|
|
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|
|
The ADC always samples at 125 MSa/s.
|
|
|
|
|
This command returns the most recent single sample, without downsampling or averaging.
|
|
|
|
|
|
|
|
|
|
### `AIN:CHn:MINMAX[:RAW]?`
|
|
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|
|
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|
|
Query: `AIN:CHn:MINMAX?` <br>
|
|
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|
|
Field _n_: channel number, in range 1 to 4. <br>
|
|
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|
|
Response: two floating point numbers separated by a space character, representing the minimum and maximum input level in Volt.
|
|
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|
|
Query: `AIN:CHn:MINMAX:RAW?` <br>
|
|
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|
|
Response: two decimal integers separated by a space character, representing the minimum and maximum raw ADC code.
|
|
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|
|
The returned values are the minimum and maximum sample values that occurred since the last reset of the range monitor.
|
|
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|
|
|
|
|
### `AIN:MINMAX:CLEAR`
|
|
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|
|
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|
|
Command: `AIN:MINMAX:CLEAR`
|
|
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|
|
|
|
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|
|
This command resets the input range monitors of all analog input channels.
|
|
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|
|
|
|
|
|
|
### `AIN:SRATE`
|
|
|
|
|
|
|
|
|
|
Command: `AIN:SRATE rate` <br>
|
|
|
|
|
Parameter _rate_: floating point number specifying the sample rate in samples per second.
|
|
|
|
|
|
|
|
|
|
This command configures the effective sample rate of the acquisition chain.
|
|
|
|
|
Valid sample rates are in range 500 to 125e6 samples per second.
|
|
|
|
|
The specified sample rate will be rounded to the nearest supported rate.
|
|
|
|
|
|
|
|
|
|
Query: `AIN:SRATE?` <br>
|
|
|
|
|
Response: floating point number representing the sample rate in samples per second.
|
|
|
|
|
|
|
|
|
|
### `AIN:SRATE:DIVISOR`
|
|
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|
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|
|
Command: `AIN:SRATE:DIVISOR divisor` <br>
|
|
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|
|
Parameter _divisor_: decimal integer specifying the downsample factor.
|
|
|
|
|
|
|
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|
|
This command configures the downsample factor of the acquisition chain.
|
|
|
|
|
Valid downsample factors are in range 1 to 250000.
|
|
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|
|
|
|
|
|
|
Query: `AIN:SRATE:DIVISOR?` <br>
|
|
|
|
|
Response: decimal integer representing the downsample factor.
|
|
|
|
|
|
|
|
|
|
**Note:** Commands `AIN:SRATE` and `AIN:SRATE:DIVISOR` are different methods to control the same internal setting.
|
|
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|
|
|
|
|
|
|
**Note:** When auto-trigger mode is selected, the downsample factor must be at least 2, or 4 if 4 channels are active.
|
|
|
|
|
In other trigger modes, the downsample factor must be at least 1, or 2 if 4 channels are active.
|
|
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|
|
|
|
|
|
|
### `AIN:SRATE:MODE`
|
|
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|
|
Command: `AIN:SRATE:MODE mode` <br>
|
|
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|
|
Parameter _mode_: downsample mode, either `DECIMATE` or `AVERAGE`.
|
|
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|
|
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|
|
This command selects downsampling by means of decimation or averaging.
|
|
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|
|
Downsampling works by collecting groups of consecutive raw ADC samples and translating each group into a single downsampled value.
|
|
|
|
|
The number of raw samples per group is determined by the downsample factor (see `AIN:SRATE:DIVISOR`).
|
|
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|
|
In mode `DECIMATE`, the first sample of a group is used as downsampled value; the other samples in the group are discarded.
|
|
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|
|
In mode `AVERAGE`, the sum of all samples in a group is used as downsampled value.
|
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|
|
Query: `AIN:SRATE:MODE?` <br>
|
|
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|
|
Response: either `DECIMATE` or `AVERAGE`.
|
|
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|
|
|
|
|
|
### `AIN:SRATE:GAIN?`
|
|
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|
|
Query: `AIN:SRATE:GAIN?` <br>
|
|
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|
|
Response: floating point number representing the effective gain factor due to downsampling.
|
|
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|
|
|
|
|
|
|
The value returned by this query depends on the downsample factor and the downsample mode.
|
|
|
|
|
|
|
|
|
|
In downsample mode `DECIMATE`, this query always returns 1.0.
|
|
|
|
|
In downsample mode `AVERAGE`, this query returns a number between 1 and 1024.
|
|
|
|
|
|
|
|
|
|
### `AIN:NSAMPLES`
|
|
|
|
|
|
|
|
|
|
Command: `AIN:NSAMPLES n` <br>
|
|
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|
|
Parameter _n_: decimal integer specifying the number of samples per channel per trigger.
|
|
|
|
|
|
|
|
|
|
This command configures the number of (downsampled) samples to collect for each trigger.
|
|
|
|
|
Valid values are from 1 to 65536.
|
|
|
|
|
|
|
|
|
|
Query: `AIN:NSAMPLES?` <br>
|
|
|
|
|
Response: decimal integer representing the number of samples per trigger.
|
|
|
|
|
|
|
|
|
|
### `AIN:TRIGGER`
|
|
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|
|
Command: `AIN:TRIGGER`
|
|
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|
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|
|
This command forces a trigger to occur, regardless of the configured trigger mode.
|
|
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|
|
|
|
|
|
|
Note that even a forced trigger may be ignored if the acquisition chain is still processing a previous trigger.
|
|
|
|
|
|
|
|
|
|
### `AIN:TRIGGER:MODE`
|
|
|
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|
|
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|
|
|
Command: `AIN:TRIGGER:MODE mode` <br>
|
|
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|
|
Parameter _mode_: trigger mode, either `NONE` or `AUTO` or `EXTERNAL` or `EXTERNAL_ONCE`.
|
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|
|
|
|
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|
|
**Note:** When trigger mode `EXTERNAL_ONCE` is selected, the trigger mode automatically changes to `NONE` as soon as a trigger occurs.
|
|
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|
|
|
|
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|
|
Query: `AIN:TRIGGER:MODE?` <br>
|
|
|
|
|
Response: active trigger mode.
|
|
|
|
|
|
|
|
|
|
### `AIN:TRIGGER:DELAY`
|
|
|
|
|
|
|
|
|
|
Command: `AIN:TRIGGER:DELAY n` <br>
|
|
|
|
|
Parameter _n_: decimal integer specifying trigger delay as a number of 8 ns cycles.
|
|
|
|
|
|
|
|
|
|
This configures a delay between trigger detection and the start of sample collection.
|
|
|
|
|
Valid values are from 0 to 65535.
|
|
|
|
|
|
|
|
|
|
Query: `AIN:TRIGGER:DELAY?` <br>
|
|
|
|
|
Response: decimal integer representing the trigger delay as a number of 8 ns cycles.
|
|
|
|
|
|
|
|
|
|
### `AIN:TRIGGER:STATUS?`
|
|
|
|
|
|
|
|
|
|
Query: `AIN:TRIGGER:STATUS?` <br>
|
|
|
|
|
Response: trigger status, either `BUSY` or `WAITING`.
|
|
|
|
|
|
|
|
|
|
This query returns `BUSY` when the acquisition chain is processing a trigger, or `WAITING` if the acquisition chain is waiting for a trigger.
|
|
|
|
|
|
|
|
|
|
### `AIN:TRIGGER:EXT:CHANNEL`
|
|
|
|
|
|
|
|
|
|
Command: `AIN:TRIGGER:EXT:CHANNEL n` <br>
|
|
|
|
|
Parameter _n_: decimal integer specifying a digital input channel, in range 0 to 3.
|
|
|
|
|
|
|
|
|
|
This command selects the digital input channel to use as external trigger.
|
|
|
|
|
|
|
|
|
|
Query: `AIN:TRIGGER:EXT:CHANNEL?` <br>
|
|
|
|
|
Response: decimal integer specifying the selected digital input channel.
|
|
|
|
|
|
|
|
|
|
### `AIN:TRIGGER:EXT:EDGE`
|
|
|
|
|
|
|
|
|
|
Command: `AIN:TRIGGER:EXT:EDGE edge` <br>
|
|
|
|
|
Parameter _edge_: trigger edge, either `RISING` or `FALLING`.
|
|
|
|
|
|
|
|
|
|
This command selects rising or falling edges in the external trigger signal.
|
|
|
|
|
|
|
|
|
|
Query: `AIN:TRIGGER:EXT:EDGE?` <br>
|
|
|
|
|
Response: either `RISING` or `FALLING`.
|
|
|
|
|
|
|
|
|
|
### `AIN:ACQUIRE:ENABLE`
|
|
|
|
|
|
|
|
|
|
Command: `AIN:ACQUIRE:ENABLE en` <br>
|
|
|
|
|
Parameter _en_: either `0` or `1`.
|
|
|
|
|
|
|
|
|
|
This command enables or disables analog acquisition.
|
|
|
|
|
When enabled, analog samples are acquired according to the configured trigger mode.
|
|
|
|
|
When disabled, all triggers are ignored and any ongoing analog acquisition stops immediately.
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Query: `AIN:ACQUIRE:ENABLE?` <br>
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Response: either `0` or `1`.
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### `TT:SAMPLE?`
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Query: `TT:SAMPLE?` <br>
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Response: array of 4 digits `0` or `1`, separated by space characters.
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This query returns the input state of all digital input channels.
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### `TT:EVENT:MASK`
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Command: `TT:EVENT:MASK mask` <br>
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Parameter _mask_: decimal integer specifying a bit mask of enabled events.
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This command configures the set of enabled timetagger events.
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The integer value of _mask_ represents an 8-bit mask.
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Each bit position denotes an event type, as follows:
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| Bit index | Value | Description |
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|-----------|-------|-------------|
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| 0 | 1 | Rising edge on digital input 0. |
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| 1 | 2 | Falling edge on digital input 0. |
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| 2 | 4 | Rising edge on digital input 1. |
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| 3 | 8 | Falling edge on digital input 1. |
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| 4 | 16 | Rising edge on digital input 2. |
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| 5 | 32 | Falling edge on digital input 2. |
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| 6 | 64 | Rising edge on digital input 3. |
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| 7 | 128 | Falling edge on digital input 3. |
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Query: `TT:EVENT:MASK?` <br>
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Response: decimal integer representing the event mask.
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### `TT:MARK`
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Command: `TT:MARK`
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This command emits a marker record in the timetagger event stream.
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### `TEMP:FPGA?`
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Query: `TEMP:FPGA?` <br>
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Response: floating point number representing the temperature in Celsius.
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The temperature is measured by the internal temperature sensor of the Zynq FPGA.
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### `IPCFG[:SAVED]`
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Command: `IPCFG DHCP` <br>
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Command: `IPCFG STATIC ipaddr netmask gateway` <br>
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Parameter _ipaddr_: IPv4 address in dotted-quad notation. <br>
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Parameter _netmask_: netmask in dotted-quad notation. <br>
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Parameter _gateway_: optional gateway address in dotted-quad notation.
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This command configures the IP address of the system.
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It expects between 1 and 4 parameters, depending on the specific address configuration.
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If address mode `DHCP` is selected, the command expects no further parameters.
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In this mode, the system attempts to get an IPv4 address from a DHCP server on the local network.
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If address mode `STATIC` is selected, the command expects 2 or 3 additional parameters to specify the address, netmask and optional gateway.
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IP addresses are specified in _dotted-quad_ notation: 4 decimal integers separated by period characters.
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The parameter _gateway_ may be omitted or specified as `0.0.0.0` to indicate that no gateway should be used.
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The command `IPCFG` takes effect immediately.
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This command does not send an `OK` response.
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Instead, all TCP connections are closed while the system prepares to change its IP address.
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Changing the IP address typically takes a few seconds.
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When the new address is active, the client may re-connect to the new IP address.
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**Note:** Configuring an invalid IP address may make the system unreachable.
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In that case, the saved IP address configuration can be restored by power-cycling the system.
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Command: `IPCFG:SAVED DHCP` <br>
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Command: `IPCFG:SAVED STATIC ipaddr netmask gateway`
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This variant of the command configures the saved IP address configuration.
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It uses the same set of parameters as `IPCFG`.
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This command has no effect on the active IP address.
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When the command completes, it sends an `OK` response and the system continues to function normally.
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The saved address configuration takes effect on the next reboot of the system.
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Query: `IPCFG?` <br>
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Query: `IPCFG:SAVED?` <br>
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Response: active or saved IP address configuration.
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### `HALT`
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Command: `HALT`
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This command iniates a shutdown of the system.
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It does not send an `OK` response.
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Instead, all TCP connections are closed while the system initiates shutdown.
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The halt command causes the system to become unresponsive to further commands.
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To recover from the halt state, the system must be power-cycled.
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### `REBOOT`
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Command: `REBOOT`
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This command initiates a system reboot.
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It does not send an `OK` response.
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Instead, all TCP connections are closed while the system initiates shutdown.
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A reboot involves a complete reset of the FPGA and the embedded ARM processor.
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The system then proceeds as if just powered on.
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