 Joris van Rantwijk
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393d87f9d2
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Add monitoring of ADC sample and min/max range
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2024-08-26 23:11:16 +02:00 |
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Joris van Rantwijk
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716d16e6a3
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Test analog acquisition chain
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2024-08-26 21:31:55 +02:00 |
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Joris van Rantwijk
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4abc2ee165
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Rework DMA to support single-beat transfers
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2024-08-24 23:04:35 +02:00 |
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Joris van Rantwijk
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5632ffc6b2
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Add VHDL for DMA write channel
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2024-08-09 20:16:53 +02:00 |
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Joris van Rantwijk
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f58343fc0f
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Test interrupt from FPGA
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2024-08-03 20:18:02 +02:00 |
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Joris van Rantwijk
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6b5f2967ac
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Add VHDL code
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2024-08-02 21:47:58 +02:00 |