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redpitaya-puzzlefw
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29 Commits 1 Branch 2 Tags 1,000 KiB
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4 Commits

Author SHA1 Message Date
Joris van Rantwijk 5632ffc6b2 Add VHDL for DMA write channel 2024-08-09 20:16:53 +02:00
Joris van Rantwijk 78c9e51587 Add Vivado non-project build script 2024-08-03 12:55:22 +02:00
Joris van Rantwijk 8d7f53e182 Disable Hierarchical synthesis of block design 
This is required for proper synthesis in non-project mode.
 2024-08-03 12:55:22 +02:00
Joris van Rantwijk a5f4e25c76 Add Vivado project 2024-08-03 12:55:15 +02:00