Add Vivado project
This commit is contained in:
parent
6b5f2967ac
commit
a5f4e25c76
|
|
@ -0,0 +1,231 @@
|
|||
#
|
||||
# $Id: red_pitaya.xdc 961 2014-01-21 11:40:39Z matej.oblak $
|
||||
#
|
||||
# @brief Red Pitaya location constraints.
|
||||
#
|
||||
# @Author Matej Oblak
|
||||
#
|
||||
# (c) Red Pitaya http://www.redpitaya.com
|
||||
#
|
||||
# Modified by Joris van Rantwijk for PuzzleFW.
|
||||
#
|
||||
|
||||
############################################################################
|
||||
# IO constraints #
|
||||
############################################################################
|
||||
|
||||
### ADC
|
||||
|
||||
# ADC data
|
||||
set_property IOSTANDARD LVCMOS18 [get_ports {adc_dat_i[*][*]}]
|
||||
set_property IOB TRUE [get_ports {adc_dat_i[*][*]}]
|
||||
|
||||
# ADC 0 data
|
||||
set_property PACKAGE_PIN V17 [get_ports {adc_dat_i[0][0]}]
|
||||
set_property PACKAGE_PIN U17 [get_ports {adc_dat_i[0][1]}]
|
||||
set_property PACKAGE_PIN Y17 [get_ports {adc_dat_i[0][2]}]
|
||||
set_property PACKAGE_PIN W16 [get_ports {adc_dat_i[0][3]}]
|
||||
set_property PACKAGE_PIN Y16 [get_ports {adc_dat_i[0][4]}]
|
||||
set_property PACKAGE_PIN W15 [get_ports {adc_dat_i[0][5]}]
|
||||
set_property PACKAGE_PIN W14 [get_ports {adc_dat_i[0][6]}]
|
||||
set_property PACKAGE_PIN Y14 [get_ports {adc_dat_i[0][7]}]
|
||||
set_property PACKAGE_PIN W13 [get_ports {adc_dat_i[0][8]}]
|
||||
set_property PACKAGE_PIN V12 [get_ports {adc_dat_i[0][9]}]
|
||||
set_property PACKAGE_PIN V13 [get_ports {adc_dat_i[0][10]}]
|
||||
set_property PACKAGE_PIN T14 [get_ports {adc_dat_i[0][11]}]
|
||||
set_property PACKAGE_PIN T15 [get_ports {adc_dat_i[0][12]}]
|
||||
set_property PACKAGE_PIN V15 [get_ports {adc_dat_i[0][13]}]
|
||||
set_property PACKAGE_PIN T16 [get_ports {adc_dat_i[0][14]}]
|
||||
set_property PACKAGE_PIN V16 [get_ports {adc_dat_i[0][15]}]
|
||||
|
||||
# ADC 1 data
|
||||
set_property PACKAGE_PIN T17 [get_ports {adc_dat_i[1][0]}]
|
||||
set_property PACKAGE_PIN R16 [get_ports {adc_dat_i[1][1]}]
|
||||
set_property PACKAGE_PIN R18 [get_ports {adc_dat_i[1][2]}]
|
||||
set_property PACKAGE_PIN P16 [get_ports {adc_dat_i[1][3]}]
|
||||
set_property PACKAGE_PIN P18 [get_ports {adc_dat_i[1][4]}]
|
||||
set_property PACKAGE_PIN N17 [get_ports {adc_dat_i[1][5]}]
|
||||
set_property PACKAGE_PIN R19 [get_ports {adc_dat_i[1][6]}]
|
||||
set_property PACKAGE_PIN T20 [get_ports {adc_dat_i[1][7]}]
|
||||
set_property PACKAGE_PIN T19 [get_ports {adc_dat_i[1][8]}]
|
||||
set_property PACKAGE_PIN U20 [get_ports {adc_dat_i[1][9]}]
|
||||
set_property PACKAGE_PIN V20 [get_ports {adc_dat_i[1][10]}]
|
||||
set_property PACKAGE_PIN W20 [get_ports {adc_dat_i[1][11]}]
|
||||
set_property PACKAGE_PIN W19 [get_ports {adc_dat_i[1][12]}]
|
||||
set_property PACKAGE_PIN Y19 [get_ports {adc_dat_i[1][13]}]
|
||||
set_property PACKAGE_PIN W18 [get_ports {adc_dat_i[1][14]}]
|
||||
set_property PACKAGE_PIN Y18 [get_ports {adc_dat_i[1][15]}]
|
||||
|
||||
set_property IOSTANDARD DIFF_HSTL_I_18 [get_ports adc_clk_i[*]]
|
||||
set_property PACKAGE_PIN U18 [get_ports adc_clk_i[1]]
|
||||
set_property PACKAGE_PIN U19 [get_ports adc_clk_i[0]]
|
||||
|
||||
# Output ADC clock
|
||||
set_property IOSTANDARD LVCMOS18 [get_ports {adc_clk_o[*]}]
|
||||
set_property SLEW FAST [get_ports {adc_clk_o[*]}]
|
||||
set_property DRIVE 8 [get_ports {adc_clk_o[*]}]
|
||||
#set_property IOB TRUE [get_ports {adc_clk_o[*]}]
|
||||
|
||||
set_property PACKAGE_PIN N20 [get_ports {adc_clk_o[0]}]
|
||||
set_property PACKAGE_PIN P20 [get_ports {adc_clk_o[1]}]
|
||||
|
||||
# ADC clock stabilizer
|
||||
set_property IOSTANDARD LVCMOS18 [get_ports adc_cdcs_o]
|
||||
set_property PACKAGE_PIN V18 [get_ports adc_cdcs_o]
|
||||
set_property SLEW FAST [get_ports adc_cdcs_o]
|
||||
set_property DRIVE 8 [get_ports adc_cdcs_o]
|
||||
|
||||
### DAC
|
||||
|
||||
# data
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports {dac_dat_o[*]}]
|
||||
set_property SLEW SLOW [get_ports {dac_dat_o[*]}]
|
||||
set_property DRIVE 4 [get_ports {dac_dat_o[*]}]
|
||||
#set_property IOB TRUE [get_ports {dac_dat_o[*]}]
|
||||
|
||||
set_property PACKAGE_PIN M19 [get_ports {dac_dat_o[0]}]
|
||||
set_property PACKAGE_PIN M20 [get_ports {dac_dat_o[1]}]
|
||||
set_property PACKAGE_PIN L19 [get_ports {dac_dat_o[2]}]
|
||||
set_property PACKAGE_PIN L20 [get_ports {dac_dat_o[3]}]
|
||||
set_property PACKAGE_PIN K19 [get_ports {dac_dat_o[4]}]
|
||||
set_property PACKAGE_PIN J19 [get_ports {dac_dat_o[5]}]
|
||||
set_property PACKAGE_PIN J20 [get_ports {dac_dat_o[6]}]
|
||||
set_property PACKAGE_PIN H20 [get_ports {dac_dat_o[7]}]
|
||||
set_property PACKAGE_PIN G19 [get_ports {dac_dat_o[8]}]
|
||||
set_property PACKAGE_PIN G20 [get_ports {dac_dat_o[9]}]
|
||||
set_property PACKAGE_PIN F19 [get_ports {dac_dat_o[10]}]
|
||||
set_property PACKAGE_PIN F20 [get_ports {dac_dat_o[11]}]
|
||||
set_property PACKAGE_PIN D20 [get_ports {dac_dat_o[12]}]
|
||||
set_property PACKAGE_PIN D19 [get_ports {dac_dat_o[13]}]
|
||||
|
||||
# control
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports dac_*_o]
|
||||
set_property SLEW FAST [get_ports dac_*_o]
|
||||
set_property DRIVE 8 [get_ports dac_*_o]
|
||||
#set_property IOB TRUE [get_ports dac_*_o]
|
||||
|
||||
set_property PACKAGE_PIN M17 [get_ports dac_wrt_o]
|
||||
set_property PACKAGE_PIN N16 [get_ports dac_sel_o]
|
||||
set_property PACKAGE_PIN M18 [get_ports dac_clk_o]
|
||||
set_property PACKAGE_PIN N15 [get_ports dac_rst_o]
|
||||
|
||||
### PWM DAC
|
||||
set_property IOSTANDARD LVCMOS18 [get_ports {dac_pwm_o[*]}]
|
||||
set_property SLEW FAST [get_ports {dac_pwm_o[*]}]
|
||||
set_property DRIVE 12 [get_ports {dac_pwm_o[*]}]
|
||||
set_property IOB TRUE [get_ports {dac_pwm_o[*]}]
|
||||
|
||||
set_property PACKAGE_PIN T10 [get_ports {dac_pwm_o[0]}]
|
||||
set_property PACKAGE_PIN T11 [get_ports {dac_pwm_o[1]}]
|
||||
set_property PACKAGE_PIN P15 [get_ports {dac_pwm_o[2]}]
|
||||
set_property PACKAGE_PIN U13 [get_ports {dac_pwm_o[3]}]
|
||||
|
||||
#### XADC
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {vinp_i[*]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {vinn_i[*]}]
|
||||
##AD0
|
||||
#set_property PACKAGE_PIN C20 [get_ports {vinp_i[1]}]
|
||||
#set_property PACKAGE_PIN B20 [get_ports {vinn_i[1]}]
|
||||
##AD1
|
||||
#set_property PACKAGE_PIN E17 [get_ports {vinp_i[2]}]
|
||||
#set_property PACKAGE_PIN D18 [get_ports {vinn_i[2]}]
|
||||
##AD8
|
||||
#set_property PACKAGE_PIN B19 [get_ports {vinp_i[0]}]
|
||||
#set_property PACKAGE_PIN A20 [get_ports {vinn_i[0]}]
|
||||
##AD9
|
||||
#set_property PACKAGE_PIN E18 [get_ports {vinp_i[3]}]
|
||||
#set_property PACKAGE_PIN E19 [get_ports {vinn_i[3]}]
|
||||
##V_0
|
||||
#set_property PACKAGE_PIN K9 [get_ports {vinp_i[4]}]
|
||||
#set_property PACKAGE_PIN L10 [get_ports {vinn_i[4]}]
|
||||
|
||||
### Expansion connector
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports {exp_p_io[*]}]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports {exp_n_io[*]}]
|
||||
set_property SLEW FAST [get_ports {exp_p_io[*]}]
|
||||
set_property SLEW FAST [get_ports {exp_n_io[*]}]
|
||||
set_property DRIVE 8 [get_ports {exp_p_io[*]}]
|
||||
set_property DRIVE 8 [get_ports {exp_n_io[*]}]
|
||||
|
||||
set_property PACKAGE_PIN G17 [get_ports {exp_p_io[0]}]
|
||||
set_property PACKAGE_PIN G18 [get_ports {exp_n_io[0]}]
|
||||
set_property PACKAGE_PIN H16 [get_ports {exp_p_io[1]}]
|
||||
set_property PACKAGE_PIN H17 [get_ports {exp_n_io[1]}]
|
||||
set_property PACKAGE_PIN J18 [get_ports {exp_p_io[2]}]
|
||||
set_property PACKAGE_PIN H18 [get_ports {exp_n_io[2]}]
|
||||
set_property PACKAGE_PIN K17 [get_ports {exp_p_io[3]}]
|
||||
set_property PACKAGE_PIN K18 [get_ports {exp_n_io[3]}]
|
||||
set_property PACKAGE_PIN L14 [get_ports {exp_p_io[4]}]
|
||||
set_property PACKAGE_PIN L15 [get_ports {exp_n_io[4]}]
|
||||
set_property PACKAGE_PIN L16 [get_ports {exp_p_io[5]}]
|
||||
set_property PACKAGE_PIN L17 [get_ports {exp_n_io[5]}]
|
||||
set_property PACKAGE_PIN K16 [get_ports {exp_p_io[6]}]
|
||||
set_property PACKAGE_PIN J16 [get_ports {exp_n_io[6]}]
|
||||
set_property PACKAGE_PIN M14 [get_ports {exp_p_io[7]}]
|
||||
set_property PACKAGE_PIN M15 [get_ports {exp_n_io[7]}]
|
||||
|
||||
#set_property PULLDOWN TRUE [get_ports {exp_p_io[0]}]
|
||||
#set_property PULLDOWN TRUE [get_ports {exp_n_io[0]}]
|
||||
#set_property PULLUP TRUE [get_ports {exp_p_io[7]}]
|
||||
#set_property PULLUP TRUE [get_ports {exp_n_io[7]}]
|
||||
|
||||
#### SATA connector
|
||||
#set_property IOSTANDARD LVCMOS18 [get_ports {daisy_p_o[*]}]
|
||||
#set_property IOSTANDARD LVCMOS18 [get_ports {daisy_n_o[*]}]
|
||||
#set_property IOSTANDARD LVCMOS18 [get_ports {daisy_p_i[*]}]
|
||||
#set_property IOSTANDARD LVCMOS18 [get_ports {daisy_n_i[*]}]
|
||||
#
|
||||
#set_property PACKAGE_PIN T12 [get_ports {daisy_p_o[0]}]
|
||||
#set_property PACKAGE_PIN U12 [get_ports {daisy_n_o[0]}]
|
||||
#set_property PACKAGE_PIN U14 [get_ports {daisy_p_o[1]}]
|
||||
#set_property PACKAGE_PIN U15 [get_ports {daisy_n_o[1]}]
|
||||
#set_property PACKAGE_PIN P14 [get_ports {daisy_p_i[0]}]
|
||||
#set_property PACKAGE_PIN R14 [get_ports {daisy_n_i[0]}]
|
||||
#set_property PACKAGE_PIN N18 [get_ports {daisy_p_i[1]}]
|
||||
#set_property PACKAGE_PIN P19 [get_ports {daisy_n_i[1]}]
|
||||
|
||||
### LED
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports {led_o[*]}]
|
||||
set_property SLEW SLOW [get_ports {led_o[*]}]
|
||||
set_property DRIVE 4 [get_ports {led_o[*]}]
|
||||
|
||||
set_property PACKAGE_PIN F16 [get_ports {led_o[0]}]
|
||||
set_property PACKAGE_PIN F17 [get_ports {led_o[1]}]
|
||||
set_property PACKAGE_PIN G15 [get_ports {led_o[2]}]
|
||||
set_property PACKAGE_PIN H15 [get_ports {led_o[3]}]
|
||||
set_property PACKAGE_PIN K14 [get_ports {led_o[4]}]
|
||||
set_property PACKAGE_PIN G14 [get_ports {led_o[5]}]
|
||||
set_property PACKAGE_PIN J15 [get_ports {led_o[6]}]
|
||||
set_property PACKAGE_PIN J14 [get_ports {led_o[7]}]
|
||||
|
||||
############################################################################
|
||||
# Clock constraints #
|
||||
############################################################################
|
||||
|
||||
#NET "adc_clk" TNM_NET = "adc_clk";
|
||||
#TIMESPEC TS_adc_clk = PERIOD "adc_clk" 125 MHz;
|
||||
|
||||
create_clock -period 8.000 -name adc_clk [get_ports adc_clk_i[1]]
|
||||
|
||||
set_input_delay -clock adc_clk 3.400 [get_ports adc_dat_i[*][*]]
|
||||
|
||||
create_clock -period 4.000 -name rx_clk [get_ports daisy_p_i[1]]
|
||||
|
||||
set_false_path -from [get_clocks adc_clk] -to [get_clocks dac_clk_o]
|
||||
set_false_path -from [get_clocks adc_clk] -to [get_clocks dac_clk_2x]
|
||||
set_false_path -from [get_clocks adc_clk] -to [get_clocks dac_clk_2p]
|
||||
set_false_path -from [get_clocks clk_fpga_0] -to [get_clocks adc_clk]
|
||||
set_false_path -from [get_clocks clk_fpga_0] -to [get_clocks dac_clk_1x]
|
||||
set_false_path -from [get_clocks clk_fpga_0] -to [get_clocks dac_clk_2x]
|
||||
set_false_path -from [get_clocks clk_fpga_0] -to [get_clocks dac_clk_2p]
|
||||
set_false_path -from [get_clocks clk_fpga_0] -to [get_clocks ser_clk]
|
||||
set_false_path -from [get_clocks clk_fpga_0] -to [get_clocks pdm_clk]
|
||||
set_false_path -from [get_clocks dac_clk_o] -to [get_clocks dac_clk_2x]
|
||||
set_false_path -from [get_clocks dac_clk_o] -to [get_clocks dac_clk_2p]
|
||||
|
||||
|
||||
############################################################################
|
||||
# Bit file settings #
|
||||
############################################################################
|
||||
|
||||
set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,522 @@
|
|||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<!-- Product Version: Vivado v2020.2 (64-bit) -->
|
||||
<!-- -->
|
||||
<!-- Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. -->
|
||||
|
||||
<Project Version="7" Minor="54" Path="/home/joris/proj/redpitaya-puzzlefw/fpga/vivado/redpitaya_puzzlefw.xpr">
|
||||
<DefaultLaunch Dir="$PRUNDIR"/>
|
||||
<Configuration>
|
||||
<Option Name="Id" Val="6bfdf9fdb55b4f6590ea35b5ab916bb3"/>
|
||||
<Option Name="Part" Val="xc7z010clg400-1"/>
|
||||
<Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
|
||||
<Option Name="CompiledLibDirXSim" Val=""/>
|
||||
<Option Name="CompiledLibDirModelSim" Val="$PCACHEDIR/compile_simlib/modelsim"/>
|
||||
<Option Name="CompiledLibDirQuesta" Val="$PCACHEDIR/compile_simlib/questa"/>
|
||||
<Option Name="CompiledLibDirIES" Val="$PCACHEDIR/compile_simlib/ies"/>
|
||||
<Option Name="CompiledLibDirXcelium" Val="$PCACHEDIR/compile_simlib/xcelium"/>
|
||||
<Option Name="CompiledLibDirVCS" Val="$PCACHEDIR/compile_simlib/vcs"/>
|
||||
<Option Name="CompiledLibDirRiviera" Val="$PCACHEDIR/compile_simlib/riviera"/>
|
||||
<Option Name="CompiledLibDirActivehdl" Val="$PCACHEDIR/compile_simlib/activehdl"/>
|
||||
<Option Name="SimulatorInstallDirModelSim" Val=""/>
|
||||
<Option Name="SimulatorInstallDirQuesta" Val=""/>
|
||||
<Option Name="SimulatorInstallDirIES" Val=""/>
|
||||
<Option Name="SimulatorInstallDirXcelium" Val=""/>
|
||||
<Option Name="SimulatorInstallDirVCS" Val=""/>
|
||||
<Option Name="SimulatorInstallDirRiviera" Val=""/>
|
||||
<Option Name="SimulatorInstallDirActiveHdl" Val=""/>
|
||||
<Option Name="SimulatorGccInstallDirModelSim" Val=""/>
|
||||
<Option Name="SimulatorGccInstallDirQuesta" Val=""/>
|
||||
<Option Name="SimulatorGccInstallDirIES" Val=""/>
|
||||
<Option Name="SimulatorGccInstallDirXcelium" Val=""/>
|
||||
<Option Name="SimulatorGccInstallDirVCS" Val=""/>
|
||||
<Option Name="SimulatorGccInstallDirRiviera" Val=""/>
|
||||
<Option Name="SimulatorGccInstallDirActiveHdl" Val=""/>
|
||||
<Option Name="TargetLanguage" Val="VHDL"/>
|
||||
<Option Name="BoardPart" Val=""/>
|
||||
<Option Name="ActiveSimSet" Val="sim_1"/>
|
||||
<Option Name="DefaultLib" Val="xil_defaultlib"/>
|
||||
<Option Name="ProjectType" Val="Default"/>
|
||||
<Option Name="IPOutputRepo" Val="$PCACHEDIR/ip"/>
|
||||
<Option Name="IPDefaultOutputPath" Val="$PGENDIR/sources_1"/>
|
||||
<Option Name="IPCachePermission" Val="read"/>
|
||||
<Option Name="IPCachePermission" Val="write"/>
|
||||
<Option Name="EnableCoreContainer" Val="FALSE"/>
|
||||
<Option Name="CreateRefXciForCoreContainers" Val="FALSE"/>
|
||||
<Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
|
||||
<Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
|
||||
<Option Name="EnableBDX" Val="FALSE"/>
|
||||
<Option Name="WTXSimLaunchSim" Val="0"/>
|
||||
<Option Name="WTModelSimLaunchSim" Val="0"/>
|
||||
<Option Name="WTQuestaLaunchSim" Val="0"/>
|
||||
<Option Name="WTIesLaunchSim" Val="0"/>
|
||||
<Option Name="WTVcsLaunchSim" Val="0"/>
|
||||
<Option Name="WTRivieraLaunchSim" Val="0"/>
|
||||
<Option Name="WTActivehdlLaunchSim" Val="0"/>
|
||||
<Option Name="WTXSimExportSim" Val="1"/>
|
||||
<Option Name="WTModelSimExportSim" Val="1"/>
|
||||
<Option Name="WTQuestaExportSim" Val="1"/>
|
||||
<Option Name="WTIesExportSim" Val="1"/>
|
||||
<Option Name="WTVcsExportSim" Val="1"/>
|
||||
<Option Name="WTRivieraExportSim" Val="1"/>
|
||||
<Option Name="WTActivehdlExportSim" Val="1"/>
|
||||
<Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
|
||||
<Option Name="XSimRadix" Val="hex"/>
|
||||
<Option Name="XSimTimeUnit" Val="ns"/>
|
||||
<Option Name="XSimArrayDisplayLimit" Val="1024"/>
|
||||
<Option Name="XSimTraceLimit" Val="65536"/>
|
||||
<Option Name="SimTypes" Val="rtl"/>
|
||||
<Option Name="SimTypes" Val="bfm"/>
|
||||
<Option Name="SimTypes" Val="tlm"/>
|
||||
<Option Name="SimTypes" Val="tlm_dpi"/>
|
||||
<Option Name="MEMEnableMemoryMapGeneration" Val="TRUE"/>
|
||||
<Option Name="DcpsUptoDate" Val="TRUE"/>
|
||||
</Configuration>
|
||||
<FileSets Version="1" Minor="31">
|
||||
<FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1" RelGenDir="$PGENDIR/sources_1">
|
||||
<Filter Type="Srcs"/>
|
||||
<File Path="$PSRCDIR/sources_1/bd/puzzlefw/puzzlefw.bd">
|
||||
<FileInfo>
|
||||
<Attr Name="ImportPath" Val="$PPRDIR/../puzzlefw/puzzlefw.bd"/>
|
||||
<Attr Name="ImportTime" Val="1722629191"/>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
<CompFileExtendedInfo CompFileName="puzzlefw.bd" FileRelPathName="ip/puzzlefw_processing_system7_0_0/puzzlefw_processing_system7_0_0.xci">
|
||||
<Proxy FileSetName="puzzlefw_processing_system7_0_0"/>
|
||||
</CompFileExtendedInfo>
|
||||
<CompFileExtendedInfo CompFileName="puzzlefw.bd" FileRelPathName="ip/puzzlefw_proc_sys_reset_0_0/puzzlefw_proc_sys_reset_0_0.xci">
|
||||
<Proxy FileSetName="puzzlefw_proc_sys_reset_0_0"/>
|
||||
</CompFileExtendedInfo>
|
||||
<CompFileExtendedInfo CompFileName="puzzlefw.bd" FileRelPathName="ip/puzzlefw_axi_apb_bridge_0_0/puzzlefw_axi_apb_bridge_0_0.xci">
|
||||
<Proxy FileSetName="puzzlefw_axi_apb_bridge_0_0"/>
|
||||
</CompFileExtendedInfo>
|
||||
<CompFileExtendedInfo CompFileName="puzzlefw.bd" FileRelPathName="ip/puzzlefw_axi_bram_ctrl_0_0/puzzlefw_axi_bram_ctrl_0_0.xci">
|
||||
<Proxy FileSetName="puzzlefw_axi_bram_ctrl_0_0"/>
|
||||
</CompFileExtendedInfo>
|
||||
<CompFileExtendedInfo CompFileName="puzzlefw.bd" FileRelPathName="ip/puzzlefw_blk_mem_gen_0_0/puzzlefw_blk_mem_gen_0_0.xci">
|
||||
<Proxy FileSetName="puzzlefw_blk_mem_gen_0_0"/>
|
||||
</CompFileExtendedInfo>
|
||||
<CompFileExtendedInfo CompFileName="puzzlefw.bd" FileRelPathName="ip/puzzlefw_auto_pc_0/puzzlefw_auto_pc_0.xci">
|
||||
<Proxy FileSetName="puzzlefw_auto_pc_0"/>
|
||||
</CompFileExtendedInfo>
|
||||
<CompFileExtendedInfo CompFileName="puzzlefw.bd" FileRelPathName="ip/puzzlefw_xbar_0/puzzlefw_xbar_0.xci">
|
||||
<Proxy FileSetName="puzzlefw_xbar_0"/>
|
||||
</CompFileExtendedInfo>
|
||||
</File>
|
||||
<File Path="$PGENDIR/sources_1/bd/puzzlefw/hdl/puzzlefw_wrapper.vhd">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../rtl/puzzlefw_pkg.vhd">
|
||||
<FileInfo SFType="VHDL2008">
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../rtl/dma_axi_master.vhd">
|
||||
<FileInfo SFType="VHDL2008">
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../rtl/registers.vhd">
|
||||
<FileInfo SFType="VHDL2008">
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../rtl/puzzlefw_top.vhd">
|
||||
<FileInfo SFType="VHDL2008">
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<Config>
|
||||
<Option Name="DesignMode" Val="RTL"/>
|
||||
<Option Name="TopModule" Val="puzzlefw_top"/>
|
||||
<Option Name="TopAutoSet" Val="TRUE"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1" RelGenDir="$PGENDIR/constrs_1">
|
||||
<Filter Type="Constrs"/>
|
||||
<File Path="$PPRDIR/../constraints/red_pitaya.xdc">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<Config>
|
||||
<Option Name="ConstrsType" Val="XDC"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1" RelGenDir="$PGENDIR/sim_1">
|
||||
<Filter Type="Srcs"/>
|
||||
<Config>
|
||||
<Option Name="DesignMode" Val="RTL"/>
|
||||
<Option Name="TopModule" Val="puzzlefw_top"/>
|
||||
<Option Name="TopLib" Val="xil_defaultlib"/>
|
||||
<Option Name="TopAutoSet" Val="TRUE"/>
|
||||
<Option Name="TransportPathDelay" Val="0"/>
|
||||
<Option Name="TransportIntDelay" Val="0"/>
|
||||
<Option Name="SelectedSimModel" Val="rtl"/>
|
||||
<Option Name="PamDesignTestbench" Val=""/>
|
||||
<Option Name="PamDutBypassFile" Val="xil_dut_bypass"/>
|
||||
<Option Name="PamSignalDriverFile" Val="xil_bypass_driver"/>
|
||||
<Option Name="PamPseudoTop" Val="pseudo_tb"/>
|
||||
<Option Name="SrcSet" Val="sources_1"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="utils_1" Type="Utils" RelSrcDir="$PSRCDIR/utils_1" RelGenDir="$PGENDIR/utils_1">
|
||||
<Filter Type="Utils"/>
|
||||
<Config>
|
||||
<Option Name="TopAutoSet" Val="TRUE"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="puzzlefw_processing_system7_0_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/puzzlefw_processing_system7_0_0" RelGenDir="$PGENDIR/puzzlefw_processing_system7_0_0">
|
||||
<Config>
|
||||
<Option Name="TopModule" Val="puzzlefw_processing_system7_0_0"/>
|
||||
<Option Name="UseBlackboxStub" Val="1"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="puzzlefw_proc_sys_reset_0_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/puzzlefw_proc_sys_reset_0_0" RelGenDir="$PGENDIR/puzzlefw_proc_sys_reset_0_0">
|
||||
<Config>
|
||||
<Option Name="TopModule" Val="puzzlefw_proc_sys_reset_0_0"/>
|
||||
<Option Name="UseBlackboxStub" Val="1"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="puzzlefw_axi_apb_bridge_0_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/puzzlefw_axi_apb_bridge_0_0" RelGenDir="$PGENDIR/puzzlefw_axi_apb_bridge_0_0">
|
||||
<Config>
|
||||
<Option Name="TopModule" Val="puzzlefw_axi_apb_bridge_0_0"/>
|
||||
<Option Name="UseBlackboxStub" Val="1"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="puzzlefw_axi_bram_ctrl_0_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/puzzlefw_axi_bram_ctrl_0_0" RelGenDir="$PGENDIR/puzzlefw_axi_bram_ctrl_0_0">
|
||||
<Config>
|
||||
<Option Name="TopModule" Val="puzzlefw_axi_bram_ctrl_0_0"/>
|
||||
<Option Name="UseBlackboxStub" Val="1"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="puzzlefw_blk_mem_gen_0_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/puzzlefw_blk_mem_gen_0_0" RelGenDir="$PGENDIR/puzzlefw_blk_mem_gen_0_0">
|
||||
<Config>
|
||||
<Option Name="TopModule" Val="puzzlefw_blk_mem_gen_0_0"/>
|
||||
<Option Name="UseBlackboxStub" Val="1"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="puzzlefw_auto_pc_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/puzzlefw_auto_pc_0" RelGenDir="$PGENDIR/puzzlefw_auto_pc_0">
|
||||
<Config>
|
||||
<Option Name="TopModule" Val="puzzlefw_auto_pc_0"/>
|
||||
<Option Name="UseBlackboxStub" Val="1"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="puzzlefw_xbar_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/puzzlefw_xbar_0" RelGenDir="$PGENDIR/puzzlefw_xbar_0">
|
||||
<Config>
|
||||
<Option Name="TopModule" Val="puzzlefw_xbar_0"/>
|
||||
<Option Name="UseBlackboxStub" Val="1"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
</FileSets>
|
||||
<Simulators>
|
||||
<Simulator Name="XSim">
|
||||
<Option Name="Description" Val="Vivado Simulator"/>
|
||||
<Option Name="CompiledLib" Val="0"/>
|
||||
</Simulator>
|
||||
<Simulator Name="ModelSim">
|
||||
<Option Name="Description" Val="ModelSim Simulator"/>
|
||||
</Simulator>
|
||||
<Simulator Name="Questa">
|
||||
<Option Name="Description" Val="Questa Advanced Simulator"/>
|
||||
</Simulator>
|
||||
<Simulator Name="IES">
|
||||
<Option Name="Description" Val="Incisive Enterprise Simulator (IES)"/>
|
||||
</Simulator>
|
||||
<Simulator Name="Xcelium">
|
||||
<Option Name="Description" Val="Xcelium Parallel Simulator"/>
|
||||
</Simulator>
|
||||
<Simulator Name="VCS">
|
||||
<Option Name="Description" Val="Verilog Compiler Simulator (VCS)"/>
|
||||
</Simulator>
|
||||
<Simulator Name="Riviera">
|
||||
<Option Name="Description" Val="Riviera-PRO Simulator"/>
|
||||
</Simulator>
|
||||
</Simulators>
|
||||
<Runs Version="1" Minor="15">
|
||||
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7z010clg400-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/synth_1" IncludeInArchive="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2020"/>
|
||||
<Step Id="synth_design"/>
|
||||
</Strategy>
|
||||
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
|
||||
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2020"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
<RQSFiles/>
|
||||
</Run>
|
||||
<Run Id="puzzlefw_processing_system7_0_0_synth_1" Type="Ft3:Synth" SrcSet="puzzlefw_processing_system7_0_0" Part="xc7z010clg400-1" ConstrsSet="puzzlefw_processing_system7_0_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/puzzlefw_processing_system7_0_0_synth_1" IncludeInArchive="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/puzzlefw_processing_system7_0_0_synth_1">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2020">
|
||||
<Desc>Vivado Synthesis Defaults</Desc>
|
||||
</StratHandle>
|
||||
<Step Id="synth_design"/>
|
||||
</Strategy>
|
||||
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
|
||||
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2020"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
<RQSFiles/>
|
||||
</Run>
|
||||
<Run Id="puzzlefw_proc_sys_reset_0_0_synth_1" Type="Ft3:Synth" SrcSet="puzzlefw_proc_sys_reset_0_0" Part="xc7z010clg400-1" ConstrsSet="puzzlefw_proc_sys_reset_0_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/puzzlefw_proc_sys_reset_0_0_synth_1" IncludeInArchive="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/puzzlefw_proc_sys_reset_0_0_synth_1">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2020">
|
||||
<Desc>Vivado Synthesis Defaults</Desc>
|
||||
</StratHandle>
|
||||
<Step Id="synth_design"/>
|
||||
</Strategy>
|
||||
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
|
||||
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2020"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
<RQSFiles/>
|
||||
</Run>
|
||||
<Run Id="puzzlefw_axi_apb_bridge_0_0_synth_1" Type="Ft3:Synth" SrcSet="puzzlefw_axi_apb_bridge_0_0" Part="xc7z010clg400-1" ConstrsSet="puzzlefw_axi_apb_bridge_0_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/puzzlefw_axi_apb_bridge_0_0_synth_1" IncludeInArchive="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/puzzlefw_axi_apb_bridge_0_0_synth_1">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2020">
|
||||
<Desc>Vivado Synthesis Defaults</Desc>
|
||||
</StratHandle>
|
||||
<Step Id="synth_design"/>
|
||||
</Strategy>
|
||||
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
|
||||
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2020"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
<RQSFiles/>
|
||||
</Run>
|
||||
<Run Id="puzzlefw_axi_bram_ctrl_0_0_synth_1" Type="Ft3:Synth" SrcSet="puzzlefw_axi_bram_ctrl_0_0" Part="xc7z010clg400-1" ConstrsSet="puzzlefw_axi_bram_ctrl_0_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/puzzlefw_axi_bram_ctrl_0_0_synth_1" IncludeInArchive="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/puzzlefw_axi_bram_ctrl_0_0_synth_1">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2020">
|
||||
<Desc>Vivado Synthesis Defaults</Desc>
|
||||
</StratHandle>
|
||||
<Step Id="synth_design"/>
|
||||
</Strategy>
|
||||
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
|
||||
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2020"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
<RQSFiles/>
|
||||
</Run>
|
||||
<Run Id="puzzlefw_blk_mem_gen_0_0_synth_1" Type="Ft3:Synth" SrcSet="puzzlefw_blk_mem_gen_0_0" Part="xc7z010clg400-1" ConstrsSet="puzzlefw_blk_mem_gen_0_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/puzzlefw_blk_mem_gen_0_0_synth_1" IncludeInArchive="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/puzzlefw_blk_mem_gen_0_0_synth_1">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2020">
|
||||
<Desc>Vivado Synthesis Defaults</Desc>
|
||||
</StratHandle>
|
||||
<Step Id="synth_design"/>
|
||||
</Strategy>
|
||||
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
|
||||
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2020"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
<RQSFiles/>
|
||||
</Run>
|
||||
<Run Id="puzzlefw_auto_pc_0_synth_1" Type="Ft3:Synth" SrcSet="puzzlefw_auto_pc_0" Part="xc7z010clg400-1" ConstrsSet="puzzlefw_auto_pc_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/puzzlefw_auto_pc_0_synth_1" IncludeInArchive="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/puzzlefw_auto_pc_0_synth_1">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2020">
|
||||
<Desc>Vivado Synthesis Defaults</Desc>
|
||||
</StratHandle>
|
||||
<Step Id="synth_design"/>
|
||||
</Strategy>
|
||||
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
|
||||
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2020"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
<RQSFiles/>
|
||||
</Run>
|
||||
<Run Id="puzzlefw_xbar_0_synth_1" Type="Ft3:Synth" SrcSet="puzzlefw_xbar_0" Part="xc7z010clg400-1" ConstrsSet="puzzlefw_xbar_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/puzzlefw_xbar_0_synth_1" IncludeInArchive="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/puzzlefw_xbar_0_synth_1">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2020">
|
||||
<Desc>Vivado Synthesis Defaults</Desc>
|
||||
</StratHandle>
|
||||
<Step Id="synth_design"/>
|
||||
</Strategy>
|
||||
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
|
||||
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2020"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
<RQSFiles/>
|
||||
</Run>
|
||||
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7z010clg400-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/impl_1" SynthRun="synth_1" IncludeInArchive="true" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2020"/>
|
||||
<Step Id="init_design"/>
|
||||
<Step Id="opt_design"/>
|
||||
<Step Id="power_opt_design"/>
|
||||
<Step Id="place_design"/>
|
||||
<Step Id="post_place_power_opt_design"/>
|
||||
<Step Id="phys_opt_design"/>
|
||||
<Step Id="route_design"/>
|
||||
<Step Id="post_route_phys_opt_design"/>
|
||||
<Step Id="write_bitstream"/>
|
||||
</Strategy>
|
||||
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
|
||||
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2020"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
<RQSFiles/>
|
||||
</Run>
|
||||
<Run Id="puzzlefw_processing_system7_0_0_impl_1" Type="Ft2:EntireDesign" Part="xc7z010clg400-1" ConstrsSet="puzzlefw_processing_system7_0_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="puzzlefw_processing_system7_0_0_synth_1" IncludeInArchive="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/puzzlefw_processing_system7_0_0_impl_1">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2020">
|
||||
<Desc>Default settings for Implementation.</Desc>
|
||||
</StratHandle>
|
||||
<Step Id="init_design"/>
|
||||
<Step Id="opt_design"/>
|
||||
<Step Id="power_opt_design"/>
|
||||
<Step Id="place_design"/>
|
||||
<Step Id="post_place_power_opt_design"/>
|
||||
<Step Id="phys_opt_design"/>
|
||||
<Step Id="route_design"/>
|
||||
<Step Id="post_route_phys_opt_design"/>
|
||||
<Step Id="write_bitstream"/>
|
||||
</Strategy>
|
||||
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2020"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
<RQSFiles/>
|
||||
</Run>
|
||||
<Run Id="puzzlefw_proc_sys_reset_0_0_impl_1" Type="Ft2:EntireDesign" Part="xc7z010clg400-1" ConstrsSet="puzzlefw_proc_sys_reset_0_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="puzzlefw_proc_sys_reset_0_0_synth_1" IncludeInArchive="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/puzzlefw_proc_sys_reset_0_0_impl_1">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2020">
|
||||
<Desc>Default settings for Implementation.</Desc>
|
||||
</StratHandle>
|
||||
<Step Id="init_design"/>
|
||||
<Step Id="opt_design"/>
|
||||
<Step Id="power_opt_design"/>
|
||||
<Step Id="place_design"/>
|
||||
<Step Id="post_place_power_opt_design"/>
|
||||
<Step Id="phys_opt_design"/>
|
||||
<Step Id="route_design"/>
|
||||
<Step Id="post_route_phys_opt_design"/>
|
||||
<Step Id="write_bitstream"/>
|
||||
</Strategy>
|
||||
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2020"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
<RQSFiles/>
|
||||
</Run>
|
||||
<Run Id="puzzlefw_axi_apb_bridge_0_0_impl_1" Type="Ft2:EntireDesign" Part="xc7z010clg400-1" ConstrsSet="puzzlefw_axi_apb_bridge_0_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="puzzlefw_axi_apb_bridge_0_0_synth_1" IncludeInArchive="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/puzzlefw_axi_apb_bridge_0_0_impl_1">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2020">
|
||||
<Desc>Default settings for Implementation.</Desc>
|
||||
</StratHandle>
|
||||
<Step Id="init_design"/>
|
||||
<Step Id="opt_design"/>
|
||||
<Step Id="power_opt_design"/>
|
||||
<Step Id="place_design"/>
|
||||
<Step Id="post_place_power_opt_design"/>
|
||||
<Step Id="phys_opt_design"/>
|
||||
<Step Id="route_design"/>
|
||||
<Step Id="post_route_phys_opt_design"/>
|
||||
<Step Id="write_bitstream"/>
|
||||
</Strategy>
|
||||
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2020"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
<RQSFiles/>
|
||||
</Run>
|
||||
<Run Id="puzzlefw_axi_bram_ctrl_0_0_impl_1" Type="Ft2:EntireDesign" Part="xc7z010clg400-1" ConstrsSet="puzzlefw_axi_bram_ctrl_0_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="puzzlefw_axi_bram_ctrl_0_0_synth_1" IncludeInArchive="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/puzzlefw_axi_bram_ctrl_0_0_impl_1">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2020">
|
||||
<Desc>Default settings for Implementation.</Desc>
|
||||
</StratHandle>
|
||||
<Step Id="init_design"/>
|
||||
<Step Id="opt_design"/>
|
||||
<Step Id="power_opt_design"/>
|
||||
<Step Id="place_design"/>
|
||||
<Step Id="post_place_power_opt_design"/>
|
||||
<Step Id="phys_opt_design"/>
|
||||
<Step Id="route_design"/>
|
||||
<Step Id="post_route_phys_opt_design"/>
|
||||
<Step Id="write_bitstream"/>
|
||||
</Strategy>
|
||||
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2020"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
<RQSFiles/>
|
||||
</Run>
|
||||
<Run Id="puzzlefw_blk_mem_gen_0_0_impl_1" Type="Ft2:EntireDesign" Part="xc7z010clg400-1" ConstrsSet="puzzlefw_blk_mem_gen_0_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="puzzlefw_blk_mem_gen_0_0_synth_1" IncludeInArchive="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/puzzlefw_blk_mem_gen_0_0_impl_1">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2020">
|
||||
<Desc>Default settings for Implementation.</Desc>
|
||||
</StratHandle>
|
||||
<Step Id="init_design"/>
|
||||
<Step Id="opt_design"/>
|
||||
<Step Id="power_opt_design"/>
|
||||
<Step Id="place_design"/>
|
||||
<Step Id="post_place_power_opt_design"/>
|
||||
<Step Id="phys_opt_design"/>
|
||||
<Step Id="route_design"/>
|
||||
<Step Id="post_route_phys_opt_design"/>
|
||||
<Step Id="write_bitstream"/>
|
||||
</Strategy>
|
||||
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2020"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
<RQSFiles/>
|
||||
</Run>
|
||||
<Run Id="puzzlefw_auto_pc_0_impl_1" Type="Ft2:EntireDesign" Part="xc7z010clg400-1" ConstrsSet="puzzlefw_auto_pc_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="puzzlefw_auto_pc_0_synth_1" IncludeInArchive="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/puzzlefw_auto_pc_0_impl_1">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2020">
|
||||
<Desc>Default settings for Implementation.</Desc>
|
||||
</StratHandle>
|
||||
<Step Id="init_design"/>
|
||||
<Step Id="opt_design"/>
|
||||
<Step Id="power_opt_design"/>
|
||||
<Step Id="place_design"/>
|
||||
<Step Id="post_place_power_opt_design"/>
|
||||
<Step Id="phys_opt_design"/>
|
||||
<Step Id="route_design"/>
|
||||
<Step Id="post_route_phys_opt_design"/>
|
||||
<Step Id="write_bitstream"/>
|
||||
</Strategy>
|
||||
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2020"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
<RQSFiles/>
|
||||
</Run>
|
||||
<Run Id="puzzlefw_xbar_0_impl_1" Type="Ft2:EntireDesign" Part="xc7z010clg400-1" ConstrsSet="puzzlefw_xbar_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="puzzlefw_xbar_0_synth_1" IncludeInArchive="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/puzzlefw_xbar_0_impl_1">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2020">
|
||||
<Desc>Default settings for Implementation.</Desc>
|
||||
</StratHandle>
|
||||
<Step Id="init_design"/>
|
||||
<Step Id="opt_design"/>
|
||||
<Step Id="power_opt_design"/>
|
||||
<Step Id="place_design"/>
|
||||
<Step Id="post_place_power_opt_design"/>
|
||||
<Step Id="phys_opt_design"/>
|
||||
<Step Id="route_design"/>
|
||||
<Step Id="post_route_phys_opt_design"/>
|
||||
<Step Id="write_bitstream"/>
|
||||
</Strategy>
|
||||
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2020"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
<RQSFiles/>
|
||||
</Run>
|
||||
</Runs>
|
||||
<Board/>
|
||||
<DashboardSummary Version="1" Minor="0">
|
||||
<Dashboards>
|
||||
<Dashboard Name="default_dashboard">
|
||||
<Gadgets>
|
||||
<Gadget Name="drc_1" Type="drc" Version="1" Row="2" Column="0">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_drc_0 "/>
|
||||
</Gadget>
|
||||
<Gadget Name="methodology_1" Type="methodology" Version="1" Row="2" Column="1">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_methodology_0 "/>
|
||||
</Gadget>
|
||||
<Gadget Name="power_1" Type="power" Version="1" Row="1" Column="0">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_power_0 "/>
|
||||
</Gadget>
|
||||
<Gadget Name="timing_1" Type="timing" Version="1" Row="0" Column="1">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_timing_summary_0 "/>
|
||||
</Gadget>
|
||||
<Gadget Name="utilization_1" Type="utilization" Version="1" Row="0" Column="0">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="synth_1#synth_1_synth_report_utilization_0 "/>
|
||||
<GadgetParam Name="RUN.STEP" Type="string" Value="synth_design"/>
|
||||
<GadgetParam Name="RUN.TYPE" Type="string" Value="synthesis"/>
|
||||
</Gadget>
|
||||
<Gadget Name="utilization_2" Type="utilization" Version="1" Row="1" Column="1">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_place_report_utilization_0 "/>
|
||||
</Gadget>
|
||||
</Gadgets>
|
||||
</Dashboard>
|
||||
<CurrentDashboard>default_dashboard</CurrentDashboard>
|
||||
</Dashboards>
|
||||
</DashboardSummary>
|
||||
</Project>
|
||||
Loading…
Reference in New Issue