From a5f4e25c764a9f06374cc90e5df12013590a853f Mon Sep 17 00:00:00 2001 From: Joris van Rantwijk Date: Fri, 2 Aug 2024 22:14:19 +0200 Subject: [PATCH] Add Vivado project --- fpga/constraints/red_pitaya.xdc | 231 ++ .../sources_1/bd/puzzlefw/puzzlefw.bd | 1944 +++++++++++++++++ fpga/vivado/redpitaya_puzzlefw.xpr | 522 +++++ 3 files changed, 2697 insertions(+) create mode 100644 fpga/constraints/red_pitaya.xdc create mode 100644 fpga/vivado/redpitaya_puzzlefw.srcs/sources_1/bd/puzzlefw/puzzlefw.bd create mode 100644 fpga/vivado/redpitaya_puzzlefw.xpr diff --git a/fpga/constraints/red_pitaya.xdc b/fpga/constraints/red_pitaya.xdc new file mode 100644 index 0000000..730e6e1 --- /dev/null +++ b/fpga/constraints/red_pitaya.xdc @@ -0,0 +1,231 @@ +# +# $Id: red_pitaya.xdc 961 2014-01-21 11:40:39Z matej.oblak $ +# +# @brief Red Pitaya location constraints. +# +# @Author Matej Oblak +# +# (c) Red Pitaya http://www.redpitaya.com +# +# Modified by Joris van Rantwijk for PuzzleFW. +# + +############################################################################ +# IO constraints # +############################################################################ + +### ADC + +# ADC data +set_property IOSTANDARD LVCMOS18 [get_ports {adc_dat_i[*][*]}] +set_property IOB TRUE [get_ports {adc_dat_i[*][*]}] + +# ADC 0 data +set_property PACKAGE_PIN V17 [get_ports {adc_dat_i[0][0]}] +set_property PACKAGE_PIN U17 [get_ports {adc_dat_i[0][1]}] +set_property PACKAGE_PIN Y17 [get_ports {adc_dat_i[0][2]}] +set_property PACKAGE_PIN W16 [get_ports {adc_dat_i[0][3]}] +set_property PACKAGE_PIN Y16 [get_ports {adc_dat_i[0][4]}] +set_property PACKAGE_PIN W15 [get_ports {adc_dat_i[0][5]}] +set_property PACKAGE_PIN W14 [get_ports {adc_dat_i[0][6]}] +set_property PACKAGE_PIN Y14 [get_ports {adc_dat_i[0][7]}] +set_property PACKAGE_PIN W13 [get_ports {adc_dat_i[0][8]}] +set_property PACKAGE_PIN V12 [get_ports {adc_dat_i[0][9]}] +set_property PACKAGE_PIN V13 [get_ports {adc_dat_i[0][10]}] +set_property PACKAGE_PIN T14 [get_ports {adc_dat_i[0][11]}] +set_property PACKAGE_PIN T15 [get_ports {adc_dat_i[0][12]}] +set_property PACKAGE_PIN V15 [get_ports {adc_dat_i[0][13]}] +set_property PACKAGE_PIN T16 [get_ports {adc_dat_i[0][14]}] +set_property PACKAGE_PIN V16 [get_ports {adc_dat_i[0][15]}] + +# ADC 1 data +set_property PACKAGE_PIN T17 [get_ports {adc_dat_i[1][0]}] +set_property PACKAGE_PIN R16 [get_ports {adc_dat_i[1][1]}] +set_property PACKAGE_PIN R18 [get_ports {adc_dat_i[1][2]}] +set_property PACKAGE_PIN P16 [get_ports {adc_dat_i[1][3]}] +set_property PACKAGE_PIN P18 [get_ports {adc_dat_i[1][4]}] +set_property PACKAGE_PIN N17 [get_ports {adc_dat_i[1][5]}] +set_property PACKAGE_PIN R19 [get_ports {adc_dat_i[1][6]}] +set_property PACKAGE_PIN T20 [get_ports {adc_dat_i[1][7]}] +set_property PACKAGE_PIN T19 [get_ports {adc_dat_i[1][8]}] +set_property PACKAGE_PIN U20 [get_ports {adc_dat_i[1][9]}] +set_property PACKAGE_PIN V20 [get_ports {adc_dat_i[1][10]}] +set_property PACKAGE_PIN W20 [get_ports {adc_dat_i[1][11]}] +set_property PACKAGE_PIN W19 [get_ports {adc_dat_i[1][12]}] +set_property PACKAGE_PIN Y19 [get_ports {adc_dat_i[1][13]}] +set_property PACKAGE_PIN W18 [get_ports {adc_dat_i[1][14]}] +set_property PACKAGE_PIN Y18 [get_ports {adc_dat_i[1][15]}] + +set_property IOSTANDARD DIFF_HSTL_I_18 [get_ports adc_clk_i[*]] +set_property PACKAGE_PIN U18 [get_ports adc_clk_i[1]] +set_property PACKAGE_PIN U19 [get_ports adc_clk_i[0]] + +# Output ADC clock +set_property IOSTANDARD LVCMOS18 [get_ports {adc_clk_o[*]}] +set_property SLEW FAST [get_ports {adc_clk_o[*]}] +set_property DRIVE 8 [get_ports {adc_clk_o[*]}] +#set_property IOB TRUE [get_ports {adc_clk_o[*]}] + +set_property PACKAGE_PIN N20 [get_ports {adc_clk_o[0]}] +set_property PACKAGE_PIN P20 [get_ports {adc_clk_o[1]}] + +# ADC clock stabilizer +set_property IOSTANDARD LVCMOS18 [get_ports adc_cdcs_o] +set_property PACKAGE_PIN V18 [get_ports adc_cdcs_o] +set_property SLEW FAST [get_ports adc_cdcs_o] +set_property DRIVE 8 [get_ports adc_cdcs_o] + +### DAC + +# data +set_property IOSTANDARD LVCMOS33 [get_ports {dac_dat_o[*]}] +set_property SLEW SLOW [get_ports {dac_dat_o[*]}] +set_property DRIVE 4 [get_ports {dac_dat_o[*]}] +#set_property IOB TRUE [get_ports {dac_dat_o[*]}] + +set_property PACKAGE_PIN M19 [get_ports {dac_dat_o[0]}] +set_property PACKAGE_PIN M20 [get_ports {dac_dat_o[1]}] +set_property PACKAGE_PIN L19 [get_ports {dac_dat_o[2]}] +set_property PACKAGE_PIN L20 [get_ports {dac_dat_o[3]}] +set_property PACKAGE_PIN K19 [get_ports {dac_dat_o[4]}] +set_property PACKAGE_PIN J19 [get_ports {dac_dat_o[5]}] +set_property PACKAGE_PIN J20 [get_ports {dac_dat_o[6]}] +set_property PACKAGE_PIN H20 [get_ports {dac_dat_o[7]}] +set_property PACKAGE_PIN G19 [get_ports {dac_dat_o[8]}] +set_property PACKAGE_PIN G20 [get_ports {dac_dat_o[9]}] +set_property PACKAGE_PIN F19 [get_ports {dac_dat_o[10]}] +set_property PACKAGE_PIN F20 [get_ports {dac_dat_o[11]}] +set_property PACKAGE_PIN D20 [get_ports {dac_dat_o[12]}] +set_property PACKAGE_PIN D19 [get_ports {dac_dat_o[13]}] + +# control +set_property IOSTANDARD LVCMOS33 [get_ports dac_*_o] +set_property SLEW FAST [get_ports dac_*_o] +set_property DRIVE 8 [get_ports dac_*_o] +#set_property IOB TRUE [get_ports dac_*_o] + +set_property PACKAGE_PIN M17 [get_ports dac_wrt_o] +set_property PACKAGE_PIN N16 [get_ports dac_sel_o] +set_property PACKAGE_PIN M18 [get_ports dac_clk_o] +set_property PACKAGE_PIN N15 [get_ports dac_rst_o] + +### PWM DAC +set_property IOSTANDARD LVCMOS18 [get_ports {dac_pwm_o[*]}] +set_property SLEW FAST [get_ports {dac_pwm_o[*]}] +set_property DRIVE 12 [get_ports {dac_pwm_o[*]}] +set_property IOB TRUE [get_ports {dac_pwm_o[*]}] + +set_property PACKAGE_PIN T10 [get_ports {dac_pwm_o[0]}] +set_property PACKAGE_PIN T11 [get_ports {dac_pwm_o[1]}] +set_property PACKAGE_PIN P15 [get_ports {dac_pwm_o[2]}] +set_property PACKAGE_PIN U13 [get_ports {dac_pwm_o[3]}] + +#### XADC +#set_property IOSTANDARD LVCMOS33 [get_ports {vinp_i[*]}] +#set_property IOSTANDARD LVCMOS33 [get_ports {vinn_i[*]}] +##AD0 +#set_property PACKAGE_PIN C20 [get_ports {vinp_i[1]}] +#set_property PACKAGE_PIN B20 [get_ports {vinn_i[1]}] +##AD1 +#set_property PACKAGE_PIN E17 [get_ports {vinp_i[2]}] +#set_property PACKAGE_PIN D18 [get_ports {vinn_i[2]}] +##AD8 +#set_property PACKAGE_PIN B19 [get_ports {vinp_i[0]}] +#set_property PACKAGE_PIN A20 [get_ports {vinn_i[0]}] +##AD9 +#set_property PACKAGE_PIN E18 [get_ports {vinp_i[3]}] +#set_property PACKAGE_PIN E19 [get_ports {vinn_i[3]}] +##V_0 +#set_property PACKAGE_PIN K9 [get_ports {vinp_i[4]}] +#set_property PACKAGE_PIN L10 [get_ports {vinn_i[4]}] + +### Expansion connector +set_property IOSTANDARD LVCMOS33 [get_ports {exp_p_io[*]}] +set_property IOSTANDARD LVCMOS33 [get_ports {exp_n_io[*]}] +set_property SLEW FAST [get_ports {exp_p_io[*]}] +set_property SLEW FAST [get_ports {exp_n_io[*]}] +set_property DRIVE 8 [get_ports {exp_p_io[*]}] +set_property DRIVE 8 [get_ports {exp_n_io[*]}] + +set_property PACKAGE_PIN G17 [get_ports {exp_p_io[0]}] +set_property PACKAGE_PIN G18 [get_ports {exp_n_io[0]}] +set_property PACKAGE_PIN H16 [get_ports {exp_p_io[1]}] +set_property PACKAGE_PIN H17 [get_ports {exp_n_io[1]}] +set_property PACKAGE_PIN J18 [get_ports {exp_p_io[2]}] +set_property PACKAGE_PIN H18 [get_ports {exp_n_io[2]}] +set_property PACKAGE_PIN K17 [get_ports {exp_p_io[3]}] +set_property PACKAGE_PIN K18 [get_ports {exp_n_io[3]}] +set_property PACKAGE_PIN L14 [get_ports {exp_p_io[4]}] +set_property PACKAGE_PIN L15 [get_ports {exp_n_io[4]}] +set_property PACKAGE_PIN L16 [get_ports {exp_p_io[5]}] +set_property PACKAGE_PIN L17 [get_ports {exp_n_io[5]}] +set_property PACKAGE_PIN K16 [get_ports {exp_p_io[6]}] +set_property PACKAGE_PIN J16 [get_ports {exp_n_io[6]}] +set_property PACKAGE_PIN M14 [get_ports {exp_p_io[7]}] +set_property PACKAGE_PIN M15 [get_ports {exp_n_io[7]}] + +#set_property PULLDOWN TRUE [get_ports {exp_p_io[0]}] +#set_property PULLDOWN TRUE [get_ports {exp_n_io[0]}] +#set_property PULLUP TRUE [get_ports {exp_p_io[7]}] +#set_property PULLUP TRUE [get_ports {exp_n_io[7]}] + +#### SATA connector +#set_property IOSTANDARD LVCMOS18 [get_ports {daisy_p_o[*]}] +#set_property IOSTANDARD LVCMOS18 [get_ports {daisy_n_o[*]}] +#set_property IOSTANDARD LVCMOS18 [get_ports {daisy_p_i[*]}] +#set_property IOSTANDARD LVCMOS18 [get_ports {daisy_n_i[*]}] +# +#set_property PACKAGE_PIN T12 [get_ports {daisy_p_o[0]}] +#set_property PACKAGE_PIN U12 [get_ports {daisy_n_o[0]}] +#set_property PACKAGE_PIN U14 [get_ports {daisy_p_o[1]}] +#set_property PACKAGE_PIN U15 [get_ports {daisy_n_o[1]}] +#set_property PACKAGE_PIN P14 [get_ports {daisy_p_i[0]}] +#set_property PACKAGE_PIN R14 [get_ports {daisy_n_i[0]}] +#set_property PACKAGE_PIN N18 [get_ports {daisy_p_i[1]}] +#set_property PACKAGE_PIN P19 [get_ports {daisy_n_i[1]}] + +### LED +set_property IOSTANDARD LVCMOS33 [get_ports {led_o[*]}] +set_property SLEW SLOW [get_ports {led_o[*]}] +set_property DRIVE 4 [get_ports {led_o[*]}] + +set_property PACKAGE_PIN F16 [get_ports {led_o[0]}] +set_property PACKAGE_PIN F17 [get_ports {led_o[1]}] +set_property PACKAGE_PIN G15 [get_ports {led_o[2]}] +set_property PACKAGE_PIN H15 [get_ports {led_o[3]}] +set_property PACKAGE_PIN K14 [get_ports {led_o[4]}] +set_property PACKAGE_PIN G14 [get_ports {led_o[5]}] +set_property PACKAGE_PIN J15 [get_ports {led_o[6]}] +set_property PACKAGE_PIN J14 [get_ports {led_o[7]}] + +############################################################################ +# Clock constraints # +############################################################################ + +#NET "adc_clk" TNM_NET = "adc_clk"; +#TIMESPEC TS_adc_clk = PERIOD "adc_clk" 125 MHz; + +create_clock -period 8.000 -name adc_clk [get_ports adc_clk_i[1]] + +set_input_delay -clock adc_clk 3.400 [get_ports adc_dat_i[*][*]] + +create_clock -period 4.000 -name rx_clk [get_ports daisy_p_i[1]] + +set_false_path -from [get_clocks adc_clk] -to [get_clocks dac_clk_o] +set_false_path -from [get_clocks adc_clk] -to [get_clocks dac_clk_2x] +set_false_path -from [get_clocks adc_clk] -to [get_clocks dac_clk_2p] +set_false_path -from [get_clocks clk_fpga_0] -to [get_clocks adc_clk] +set_false_path -from [get_clocks clk_fpga_0] -to [get_clocks dac_clk_1x] +set_false_path -from [get_clocks clk_fpga_0] -to [get_clocks dac_clk_2x] +set_false_path -from [get_clocks clk_fpga_0] -to [get_clocks dac_clk_2p] +set_false_path -from [get_clocks clk_fpga_0] -to [get_clocks ser_clk] +set_false_path -from [get_clocks clk_fpga_0] -to [get_clocks pdm_clk] +set_false_path -from [get_clocks dac_clk_o] -to [get_clocks dac_clk_2x] +set_false_path -from [get_clocks dac_clk_o] -to [get_clocks dac_clk_2p] + + +############################################################################ +# Bit file settings # +############################################################################ + +set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design] diff --git a/fpga/vivado/redpitaya_puzzlefw.srcs/sources_1/bd/puzzlefw/puzzlefw.bd b/fpga/vivado/redpitaya_puzzlefw.srcs/sources_1/bd/puzzlefw/puzzlefw.bd new file mode 100644 index 0000000..88fb660 --- /dev/null +++ b/fpga/vivado/redpitaya_puzzlefw.srcs/sources_1/bd/puzzlefw/puzzlefw.bd @@ -0,0 +1,1944 @@ +{ + "design": { + "design_info": { + "boundary_crc": "0x3DCD19FE44770B59", + "device": "xc7z010clg400-1", + "gen_directory": "../../../../redpitaya_puzzlefw.gen/sources_1/bd/puzzlefw", + "name": "puzzlefw", + "rev_ctrl_bd_flag": "RevCtrlBdOff", + "synth_flow_mode": "Hierarchical", + "tool_version": "2020.2", + "validated": "true" + }, + "design_tree": { + "processing_system7_0": "", + "proc_sys_reset_0": "", + "axi_interconnect_0": { + "xbar": "", + "s00_couplers": { + "auto_pc": "" + }, + "m00_couplers": {}, + "m01_couplers": {} + }, + "axi_apb_bridge_0": "", + "axi_bram_ctrl_0": "", + "blk_mem_gen_0": "" + }, + "interface_ports": { + "DDR_0": { + "mode": "Master", + "vlnv": "xilinx.com:interface:ddrx_rtl:1.0", + "parameters": { + "AXI_ARBITRATION_SCHEME": { + "value": "TDM", + "value_src": "default" + }, + "BURST_LENGTH": { + "value": "8", + "value_src": "default" + }, + "CAN_DEBUG": { + "value": "false", + "value_src": "default" + }, + "CAS_LATENCY": { + "value": "11", + "value_src": "default" + }, + "CAS_WRITE_LATENCY": { + "value": "11", + "value_src": "default" + }, + "CS_ENABLED": { + "value": "true", + "value_src": "default" + }, + "DATA_MASK_ENABLED": { + "value": "true", + "value_src": "default" + }, + "DATA_WIDTH": { + "value": "8", + "value_src": "default" + }, + "MEMORY_TYPE": { + "value": "COMPONENTS", + "value_src": "default" + }, + "MEM_ADDR_MAP": { + "value": "ROW_COLUMN_BANK", + "value_src": "default" + }, + "SLOT": { + "value": "Single", + "value_src": "default" + }, + "TIMEPERIOD_PS": { + "value": "1250", + "value_src": "default" + } + } + }, + "FIXED_IO_0": { + "mode": "Master", + "vlnv": "xilinx.com:display_processing_system7:fixedio_rtl:1.0", + "parameters": { + "CAN_DEBUG": { + "value": "false", + "value_src": "default" + } + } + }, + "APB_M_0": { + "mode": "Master", + "vlnv": "xilinx.com:interface:apb_rtl:1.0", + "memory_map_ref": "APB_M_0" + }, + "S_AXI_HP0_0": { + "mode": "Slave", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0", + "address_space_ref": "S_AXI_HP0_0", + "base_address": { + "minimum": "0x00000000", + "maximum": "0xFFFFFFFF", + "width": "32" + }, + "parameters": { + "ADDR_WIDTH": { + "value": "32" + }, + "ARUSER_WIDTH": { + "value": "0" + }, + "AWUSER_WIDTH": { + "value": "0" + }, + "BUSER_WIDTH": { + "value": "0" + }, + "CLK_DOMAIN": { + "value": "puzzlefw_sys_clk", + "value_src": "default" + }, + "DATA_WIDTH": { + "value": "64" + }, + "FREQ_HZ": { + "value": "125000000" + }, + "HAS_BRESP": { + "value": "1" + }, + "HAS_BURST": { + "value": "1" + }, + "HAS_CACHE": { + "value": "1" + }, + "HAS_LOCK": { + "value": "1" + }, + "HAS_PROT": { + "value": "1" + }, + "HAS_QOS": { + "value": "1" + }, + "HAS_REGION": { + "value": "0" + }, + "HAS_RRESP": { + "value": "1" + }, + "HAS_WSTRB": { + "value": "1" + }, + "ID_WIDTH": { + "value": "6" + }, + "INSERT_VIP": { + "value": "0", + "value_src": "default" + }, + "MAX_BURST_LENGTH": { + "value": "16" + }, + "NUM_READ_OUTSTANDING": { + "value": "8" + }, + "NUM_READ_THREADS": { + "value": "1" + }, + "NUM_WRITE_OUTSTANDING": { + "value": "8" + }, + "NUM_WRITE_THREADS": { + "value": "1" + }, + "PHASE": { + "value": "0.000", + "value_src": "default" + }, + "PROTOCOL": { + "value": "AXI3" + }, + "READ_WRITE_MODE": { + "value": "READ_WRITE" + }, + "RUSER_BITS_PER_BYTE": { + "value": "0" + }, + "RUSER_WIDTH": { + "value": "0" + }, + "SUPPORTS_NARROW_BURST": { + "value": "0" + }, + "WUSER_BITS_PER_BYTE": { + "value": "0" + }, + "WUSER_WIDTH": { + "value": "0" + } + } + } + }, + "ports": { + "IRQ_F2P": { + "type": "intr", + "direction": "I", + "left": "7", + "right": "0", + "parameters": { + "PortWidth": { + "value": "8" + }, + "SENSITIVITY": { + "value": "LEVEL_HIGH", + "value_src": "default" + } + } + }, + "peripheral_reset_0": { + "type": "rst", + "direction": "O", + "left": "0", + "right": "0", + "parameters": { + "INSERT_VIP": { + "value": "0", + "value_src": "default" + }, + "POLARITY": { + "value": "ACTIVE_HIGH", + "value_src": "const_prop" + } + } + }, + "sys_clk": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_BUSIF": { + "value": "S_AXI_HP0_0" + }, + "CLK_DOMAIN": { + "value": "puzzlefw_sys_clk", + "value_src": "default" + }, + "FREQ_HZ": { + "value": "125000000" + }, + "FREQ_TOLERANCE_HZ": { + "value": "0", + "value_src": "default" + }, + "INSERT_VIP": { + "value": "0", + "value_src": "default" + }, + "PHASE": { + "value": "0.000", + "value_src": "default" + } + } + }, + "ps_fclk": { + "type": "clk", + "direction": "O", + "parameters": { + "CLK_DOMAIN": { + "value": "puzzlefw_processing_system7_0_0_FCLK_CLK0", + "value_src": "default_prop" + }, + "FREQ_HZ": { + "value": "125000000", + "value_src": "user_prop" + }, + "FREQ_TOLERANCE_HZ": { + "value": "0", + "value_src": "default" + }, + "INSERT_VIP": { + "value": "0", + "value_src": "default" + }, + "PHASE": { + "value": "0.000", + "value_src": "default" + } + } + } + }, + "components": { + "processing_system7_0": { + "vlnv": "xilinx.com:ip:processing_system7:5.5", + "xci_name": "puzzlefw_processing_system7_0_0", + "xci_path": "ip/puzzlefw_processing_system7_0_0/puzzlefw_processing_system7_0_0.xci", + "inst_hier_path": "processing_system7_0", + "parameters": { + "PCW_ACT_APU_PERIPHERAL_FREQMHZ": { + "value": "666.666687" + }, + "PCW_ACT_CAN_PERIPHERAL_FREQMHZ": { + "value": "10.000000" + }, + "PCW_ACT_DCI_PERIPHERAL_FREQMHZ": { + "value": "10.158730" + }, + "PCW_ACT_ENET0_PERIPHERAL_FREQMHZ": { + "value": "125.000000" + }, + "PCW_ACT_ENET1_PERIPHERAL_FREQMHZ": { + "value": "10.000000" + }, + "PCW_ACT_FPGA0_PERIPHERAL_FREQMHZ": { + "value": "125.000000" + }, + "PCW_ACT_FPGA1_PERIPHERAL_FREQMHZ": { + "value": "10.000000" + }, + "PCW_ACT_FPGA2_PERIPHERAL_FREQMHZ": { + "value": "10.000000" + }, + "PCW_ACT_FPGA3_PERIPHERAL_FREQMHZ": { + "value": "10.000000" + }, + "PCW_ACT_PCAP_PERIPHERAL_FREQMHZ": { + "value": "200.000000" + }, + "PCW_ACT_QSPI_PERIPHERAL_FREQMHZ": { + "value": "125.000000" + }, + "PCW_ACT_SDIO_PERIPHERAL_FREQMHZ": { + "value": "100.000000" + }, + "PCW_ACT_SMC_PERIPHERAL_FREQMHZ": { + "value": "10.000000" + }, + "PCW_ACT_SPI_PERIPHERAL_FREQMHZ": { + "value": "200.000000" + }, + "PCW_ACT_TPIU_PERIPHERAL_FREQMHZ": { + "value": "200.000000" + }, + "PCW_ACT_TTC0_CLK0_PERIPHERAL_FREQMHZ": { + "value": "111.111115" + }, + "PCW_ACT_TTC0_CLK1_PERIPHERAL_FREQMHZ": { + "value": "111.111115" + }, + "PCW_ACT_TTC0_CLK2_PERIPHERAL_FREQMHZ": { + "value": "111.111115" + }, + "PCW_ACT_TTC1_CLK0_PERIPHERAL_FREQMHZ": { + "value": "111.111115" + }, + "PCW_ACT_TTC1_CLK1_PERIPHERAL_FREQMHZ": { + "value": "111.111115" + }, + "PCW_ACT_TTC1_CLK2_PERIPHERAL_FREQMHZ": { + "value": "111.111115" + }, + "PCW_ACT_UART_PERIPHERAL_FREQMHZ": { + "value": "100.000000" + }, + "PCW_ACT_WDT_PERIPHERAL_FREQMHZ": { + "value": "111.111115" + }, + "PCW_CLK0_FREQ": { + "value": "125000000" + }, + "PCW_CLK1_FREQ": { + "value": "10000000" + }, + "PCW_CLK2_FREQ": { + "value": "10000000" + }, + "PCW_CLK3_FREQ": { + "value": "10000000" + }, + "PCW_DDR_RAM_HIGHADDR": { + "value": "0x1FFFFFFF" + }, + "PCW_ENET0_ENET0_IO": { + "value": "MIO 16 .. 27" + }, + "PCW_ENET0_GRP_MDIO_ENABLE": { + "value": "1" + }, + "PCW_ENET0_GRP_MDIO_IO": { + "value": "MIO 52 .. 53" + }, + "PCW_ENET0_PERIPHERAL_CLKSRC": { + "value": "IO PLL" + }, + "PCW_ENET0_PERIPHERAL_ENABLE": { + "value": "1" + }, + "PCW_ENET0_PERIPHERAL_FREQMHZ": { + "value": "1000 Mbps" + }, + "PCW_ENET0_RESET_ENABLE": { + "value": "0" + }, + "PCW_ENET_RESET_ENABLE": { + "value": "1" + }, + "PCW_ENET_RESET_SELECT": { + "value": "Share reset pin" + }, + "PCW_EN_CLK1_PORT": { + "value": "0" + }, + "PCW_EN_EMIO_CD_SDIO0": { + "value": "0" + }, + "PCW_EN_EMIO_ENET0": { + "value": "0" + }, + "PCW_EN_EMIO_GPIO": { + "value": "1" + }, + "PCW_EN_EMIO_I2C0": { + "value": "0" + }, + "PCW_EN_EMIO_SPI0": { + "value": "1" + }, + "PCW_EN_EMIO_SPI1": { + "value": "0" + }, + "PCW_EN_EMIO_TTC0": { + "value": "1" + }, + "PCW_EN_EMIO_UART0": { + "value": "0" + }, + "PCW_EN_EMIO_WP_SDIO0": { + "value": "0" + }, + "PCW_EN_ENET0": { + "value": "1" + }, + "PCW_EN_GPIO": { + "value": "1" + }, + "PCW_EN_I2C0": { + "value": "1" + }, + "PCW_EN_QSPI": { + "value": "1" + }, + "PCW_EN_RST1_PORT": { + "value": "0" + }, + "PCW_EN_SDIO0": { + "value": "1" + }, + "PCW_EN_SPI0": { + "value": "1" + }, + "PCW_EN_SPI1": { + "value": "1" + }, + "PCW_EN_TTC0": { + "value": "1" + }, + "PCW_EN_UART0": { + "value": "1" + }, + "PCW_EN_UART1": { + "value": "1" + }, + "PCW_EN_USB0": { + "value": "1" + }, + "PCW_FCLK0_PERIPHERAL_CLKSRC": { + "value": "IO PLL" + }, + "PCW_FPGA0_PERIPHERAL_FREQMHZ": { + "value": "125" + }, + "PCW_FPGA1_PERIPHERAL_FREQMHZ": { + "value": "250" + }, + "PCW_FPGA_FCLK0_ENABLE": { + "value": "1" + }, + "PCW_GPIO_EMIO_GPIO_ENABLE": { + "value": "1" + }, + "PCW_GPIO_EMIO_GPIO_IO": { + "value": "24" + }, + "PCW_GPIO_EMIO_GPIO_WIDTH": { + "value": "24" + }, + "PCW_GPIO_MIO_GPIO_ENABLE": { + "value": "1" + }, + "PCW_GPIO_MIO_GPIO_IO": { + "value": "MIO" + }, + "PCW_I2C0_GRP_INT_ENABLE": { + "value": "0" + }, + "PCW_I2C0_I2C0_IO": { + "value": "MIO 50 .. 51" + }, + "PCW_I2C0_PERIPHERAL_ENABLE": { + "value": "1" + }, + "PCW_I2C0_RESET_ENABLE": { + "value": "0" + }, + "PCW_I2C_PERIPHERAL_FREQMHZ": { + "value": "111.111115" + }, + "PCW_I2C_RESET_ENABLE": { + "value": "1" + }, + "PCW_I2C_RESET_SELECT": { + "value": "Share reset pin" + }, + "PCW_IRQ_F2P_INTR": { + "value": "1" + }, + "PCW_MIO_0_IOTYPE": { + "value": "LVCMOS 3.3V" + }, + "PCW_MIO_0_PULLUP": { + "value": "enabled" + }, + "PCW_MIO_0_SLEW": { + "value": "slow" + }, + "PCW_MIO_10_IOTYPE": { + "value": "LVCMOS 3.3V" + }, + "PCW_MIO_10_PULLUP": { + "value": "enabled" + }, + "PCW_MIO_10_SLEW": { + "value": "slow" + }, + "PCW_MIO_11_IOTYPE": { + "value": "LVCMOS 3.3V" + }, + "PCW_MIO_11_PULLUP": { + "value": "enabled" + }, + "PCW_MIO_11_SLEW": { + "value": "slow" + }, + "PCW_MIO_12_IOTYPE": { + "value": "LVCMOS 3.3V" + }, + "PCW_MIO_12_PULLUP": { + "value": "enabled" + }, + "PCW_MIO_12_SLEW": { + "value": "slow" + }, + "PCW_MIO_13_IOTYPE": { + "value": "LVCMOS 3.3V" + }, + "PCW_MIO_13_PULLUP": { + "value": "enabled" + }, + "PCW_MIO_13_SLEW": { + "value": "slow" + }, + "PCW_MIO_14_IOTYPE": { + "value": "LVCMOS 3.3V" + }, + "PCW_MIO_14_PULLUP": { + "value": "enabled" + }, + "PCW_MIO_14_SLEW": { + "value": "slow" + }, + "PCW_MIO_15_IOTYPE": { + "value": "LVCMOS 3.3V" + }, + "PCW_MIO_15_PULLUP": { + "value": "enabled" + }, + "PCW_MIO_15_SLEW": { + "value": "slow" + }, + "PCW_MIO_16_IOTYPE": { + "value": "LVCMOS 2.5V" + }, + "PCW_MIO_16_PULLUP": { + "value": "enabled" + }, + "PCW_MIO_16_SLEW": { + "value": "fast" + }, + "PCW_MIO_17_IOTYPE": { + "value": "LVCMOS 2.5V" + }, + "PCW_MIO_17_PULLUP": { + "value": "enabled" + }, + "PCW_MIO_17_SLEW": { + "value": "fast" + }, + "PCW_MIO_18_IOTYPE": { + "value": "LVCMOS 2.5V" + }, + "PCW_MIO_18_PULLUP": { + "value": "enabled" + }, + "PCW_MIO_18_SLEW": { + "value": "fast" + }, + "PCW_MIO_19_IOTYPE": { + "value": "LVCMOS 2.5V" + }, + "PCW_MIO_19_PULLUP": { + "value": "enabled" + }, + "PCW_MIO_19_SLEW": { + "value": "fast" + }, + "PCW_MIO_1_IOTYPE": { + "value": "LVCMOS 3.3V" + }, + "PCW_MIO_1_PULLUP": { + "value": "enabled" + }, + "PCW_MIO_1_SLEW": { + "value": "slow" + }, + "PCW_MIO_20_IOTYPE": { + "value": "LVCMOS 2.5V" + }, + "PCW_MIO_20_PULLUP": { + "value": "enabled" + }, + "PCW_MIO_20_SLEW": { + "value": "fast" + }, + "PCW_MIO_21_IOTYPE": { + "value": "LVCMOS 2.5V" + }, + "PCW_MIO_21_PULLUP": { + "value": "enabled" + }, + "PCW_MIO_21_SLEW": { + "value": "fast" + }, + "PCW_MIO_22_IOTYPE": { + "value": "LVCMOS 2.5V" + }, + "PCW_MIO_22_PULLUP": { + "value": "enabled" + }, + "PCW_MIO_22_SLEW": { + "value": "fast" + }, + "PCW_MIO_23_IOTYPE": { + "value": "LVCMOS 2.5V" + }, + "PCW_MIO_23_PULLUP": { + "value": "enabled" + }, + "PCW_MIO_23_SLEW": { + "value": "fast" + }, + "PCW_MIO_24_IOTYPE": { + "value": "LVCMOS 2.5V" + }, + "PCW_MIO_24_PULLUP": { + "value": "enabled" + }, + "PCW_MIO_24_SLEW": { + "value": "fast" + }, + "PCW_MIO_25_IOTYPE": { + "value": "LVCMOS 2.5V" + }, + "PCW_MIO_25_PULLUP": { + "value": "enabled" + }, + "PCW_MIO_25_SLEW": { + "value": "fast" + }, + "PCW_MIO_26_IOTYPE": { + "value": "LVCMOS 2.5V" + }, + "PCW_MIO_26_PULLUP": { + "value": "enabled" + }, + "PCW_MIO_26_SLEW": { + "value": "fast" + }, + "PCW_MIO_27_IOTYPE": { + "value": "LVCMOS 2.5V" + }, + "PCW_MIO_27_PULLUP": { + "value": "enabled" + }, + "PCW_MIO_27_SLEW": { + "value": "fast" + }, + "PCW_MIO_28_IOTYPE": { + "value": "LVCMOS 2.5V" + }, + "PCW_MIO_28_PULLUP": { + "value": "enabled" + }, + "PCW_MIO_28_SLEW": { + "value": "fast" + }, + "PCW_MIO_29_IOTYPE": { + "value": "LVCMOS 2.5V" + }, + "PCW_MIO_29_PULLUP": { + "value": "enabled" + }, + "PCW_MIO_29_SLEW": { + "value": "fast" + }, + "PCW_MIO_2_IOTYPE": { + "value": "LVCMOS 3.3V" + }, + "PCW_MIO_2_SLEW": { + "value": "slow" + }, + "PCW_MIO_30_IOTYPE": { + "value": "LVCMOS 2.5V" + }, + "PCW_MIO_30_PULLUP": { + "value": "enabled" + }, + "PCW_MIO_30_SLEW": { + "value": "fast" + }, + "PCW_MIO_31_IOTYPE": { + "value": "LVCMOS 2.5V" + }, + "PCW_MIO_31_PULLUP": { + "value": "enabled" + }, + "PCW_MIO_31_SLEW": { + "value": "fast" + }, + "PCW_MIO_32_IOTYPE": { + "value": "LVCMOS 2.5V" + }, + "PCW_MIO_32_PULLUP": { + "value": "enabled" + }, + "PCW_MIO_32_SLEW": { + "value": "fast" + }, + "PCW_MIO_33_IOTYPE": { + "value": "LVCMOS 2.5V" + }, + "PCW_MIO_33_PULLUP": { + "value": "enabled" + }, + "PCW_MIO_33_SLEW": { + "value": "fast" + }, + "PCW_MIO_34_IOTYPE": { + "value": "LVCMOS 2.5V" + }, + "PCW_MIO_34_PULLUP": { + "value": "enabled" + }, + "PCW_MIO_34_SLEW": { + "value": "fast" + }, + "PCW_MIO_35_IOTYPE": { + "value": "LVCMOS 2.5V" + }, + "PCW_MIO_35_PULLUP": { + "value": "enabled" + }, + "PCW_MIO_35_SLEW": { + "value": "fast" + }, + "PCW_MIO_36_IOTYPE": { + "value": "LVCMOS 2.5V" + }, + "PCW_MIO_36_PULLUP": { + "value": "enabled" + }, + "PCW_MIO_36_SLEW": { + "value": "fast" + }, + "PCW_MIO_37_IOTYPE": { + "value": "LVCMOS 2.5V" + }, + "PCW_MIO_37_PULLUP": { + "value": "enabled" + }, + "PCW_MIO_37_SLEW": { + "value": "fast" + }, + "PCW_MIO_38_IOTYPE": { + "value": "LVCMOS 2.5V" + }, + "PCW_MIO_38_PULLUP": { + "value": "enabled" + }, + "PCW_MIO_38_SLEW": { + "value": "fast" + }, + "PCW_MIO_39_IOTYPE": { + "value": "LVCMOS 2.5V" + }, + "PCW_MIO_39_PULLUP": { + "value": "enabled" + }, + "PCW_MIO_39_SLEW": { + "value": "fast" + }, + "PCW_MIO_3_IOTYPE": { + "value": "LVCMOS 3.3V" + }, + "PCW_MIO_3_SLEW": { + "value": "slow" + }, + "PCW_MIO_40_IOTYPE": { + "value": "LVCMOS 2.5V" + }, + "PCW_MIO_40_PULLUP": { + "value": "enabled" + }, + "PCW_MIO_40_SLEW": { + "value": "slow" + }, + "PCW_MIO_41_IOTYPE": { + "value": "LVCMOS 2.5V" + }, + "PCW_MIO_41_PULLUP": { + "value": "enabled" + }, + "PCW_MIO_41_SLEW": { + "value": "slow" + }, + "PCW_MIO_42_IOTYPE": { + "value": "LVCMOS 2.5V" + }, + "PCW_MIO_42_PULLUP": { + "value": "enabled" + }, + "PCW_MIO_42_SLEW": { + "value": "slow" + }, + "PCW_MIO_43_IOTYPE": { + "value": "LVCMOS 2.5V" + }, + "PCW_MIO_43_PULLUP": { + "value": "enabled" + }, + "PCW_MIO_43_SLEW": { + "value": "slow" + }, + "PCW_MIO_44_IOTYPE": { + "value": "LVCMOS 2.5V" + }, + "PCW_MIO_44_PULLUP": { + "value": "enabled" + }, + "PCW_MIO_44_SLEW": { + "value": "slow" + }, + "PCW_MIO_45_IOTYPE": { + "value": "LVCMOS 2.5V" + }, + "PCW_MIO_45_PULLUP": { + "value": "enabled" + }, + "PCW_MIO_45_SLEW": { + "value": "slow" + }, + "PCW_MIO_46_IOTYPE": { + "value": "LVCMOS 2.5V" + }, + "PCW_MIO_46_PULLUP": { + "value": "enabled" + }, + "PCW_MIO_46_SLEW": { + "value": "slow" + }, + "PCW_MIO_47_IOTYPE": { + "value": "LVCMOS 2.5V" + }, + "PCW_MIO_47_PULLUP": { + "value": "enabled" + }, + "PCW_MIO_47_SLEW": { + "value": "slow" + }, + "PCW_MIO_48_IOTYPE": { + "value": "LVCMOS 2.5V" + }, + "PCW_MIO_48_PULLUP": { + "value": "enabled" + }, + "PCW_MIO_48_SLEW": { + "value": "slow" + }, + "PCW_MIO_49_IOTYPE": { + "value": "LVCMOS 2.5V" + }, + "PCW_MIO_49_PULLUP": { + "value": "enabled" + }, + "PCW_MIO_49_SLEW": { + "value": "slow" + }, + "PCW_MIO_4_IOTYPE": { + "value": "LVCMOS 3.3V" + }, + "PCW_MIO_4_SLEW": { + "value": "slow" + }, + "PCW_MIO_50_IOTYPE": { + "value": "LVCMOS 2.5V" + }, + "PCW_MIO_50_PULLUP": { + "value": "enabled" + }, + "PCW_MIO_50_SLEW": { + "value": "slow" + }, + "PCW_MIO_51_IOTYPE": { + "value": "LVCMOS 2.5V" + }, + "PCW_MIO_51_PULLUP": { + "value": "enabled" + }, + "PCW_MIO_51_SLEW": { + "value": "slow" + }, + "PCW_MIO_52_IOTYPE": { + "value": "LVCMOS 2.5V" + }, + "PCW_MIO_52_PULLUP": { + "value": "enabled" + }, + "PCW_MIO_52_SLEW": { + "value": "slow" + }, + "PCW_MIO_53_IOTYPE": { + "value": "LVCMOS 2.5V" + }, + "PCW_MIO_53_PULLUP": { + "value": "enabled" + }, + "PCW_MIO_53_SLEW": { + "value": "slow" + }, + "PCW_MIO_5_IOTYPE": { + "value": "LVCMOS 3.3V" + }, + "PCW_MIO_5_SLEW": { + "value": "slow" + }, + "PCW_MIO_6_IOTYPE": { + "value": "LVCMOS 3.3V" + }, + "PCW_MIO_6_SLEW": { + "value": "slow" + }, + "PCW_MIO_7_IOTYPE": { + "value": "LVCMOS 3.3V" + }, + "PCW_MIO_7_SLEW": { + "value": "slow" + }, + "PCW_MIO_8_IOTYPE": { + "value": "LVCMOS 3.3V" + }, + "PCW_MIO_8_SLEW": { + "value": "slow" + }, + "PCW_MIO_9_IOTYPE": { + "value": "LVCMOS 3.3V" + }, + "PCW_MIO_9_PULLUP": { + "value": "enabled" + }, + "PCW_MIO_9_SLEW": { + "value": "slow" + }, + "PCW_MIO_TREE_PERIPHERALS": { + "value": "SD 0#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#GPIO#UART 1#UART 1#SPI 1#SPI 1#SPI 1#SPI 1#UART 0#UART 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#SD 0#SD 0#SD 0#SD 0#SD 0#SD 0#SD 0#SD 0#USB Reset#GPIO#I2C 0#I2C 0#Enet 0#Enet 0" + }, + "PCW_MIO_TREE_SIGNALS": { + "value": "sdio0_pow#qspi0_ss_b#qspi0_io[0]#qspi0_io[1]#qspi0_io[2]#qspi0_io[3]/HOLD_B#qspi0_sclk#gpio[7]#tx#rx#mosi#miso#sclk#ss[0]#rx#tx#tx_clk#txd[0]#txd[1]#txd[2]#txd[3]#tx_ctl#rx_clk#rxd[0]#rxd[1]#rxd[2]#rxd[3]#rx_ctl#data[4]#dir#stp#nxt#data[0]#data[1]#data[2]#data[3]#clk#data[5]#data[6]#data[7]#clk#cmd#data[0]#data[1]#data[2]#data[3]#cd#wp#reset#gpio[49]#scl#sda#mdc#mdio" + }, + "PCW_PRESET_BANK1_VOLTAGE": { + "value": "LVCMOS 2.5V" + }, + "PCW_QSPI_GRP_FBCLK_ENABLE": { + "value": "0" + }, + "PCW_QSPI_GRP_IO1_ENABLE": { + "value": "0" + }, + "PCW_QSPI_GRP_SINGLE_SS_ENABLE": { + "value": "1" + }, + "PCW_QSPI_GRP_SINGLE_SS_IO": { + "value": "MIO 1 .. 6" + }, + "PCW_QSPI_GRP_SS1_ENABLE": { + "value": "0" + }, + "PCW_QSPI_INTERNAL_HIGHADDRESS": { + "value": "0xFCFFFFFF" + }, + "PCW_QSPI_PERIPHERAL_ENABLE": { + "value": "1" + }, + "PCW_QSPI_PERIPHERAL_FREQMHZ": { + "value": "125" + }, + "PCW_QSPI_QSPI_IO": { + "value": "MIO 1 .. 6" + }, + "PCW_SD0_GRP_CD_ENABLE": { + "value": "1" + }, + "PCW_SD0_GRP_CD_IO": { + "value": "MIO 46" + }, + "PCW_SD0_GRP_POW_ENABLE": { + "value": "1" + }, + "PCW_SD0_GRP_POW_IO": { + "value": "MIO 0" + }, + "PCW_SD0_GRP_WP_ENABLE": { + "value": "1" + }, + "PCW_SD0_GRP_WP_IO": { + "value": "MIO 47" + }, + "PCW_SD0_PERIPHERAL_ENABLE": { + "value": "1" + }, + "PCW_SD0_SD0_IO": { + "value": "MIO 40 .. 45" + }, + "PCW_SDIO_PERIPHERAL_FREQMHZ": { + "value": "100" + }, + "PCW_SDIO_PERIPHERAL_VALID": { + "value": "1" + }, + "PCW_SINGLE_QSPI_DATA_MODE": { + "value": "x4" + }, + "PCW_SPI0_PERIPHERAL_ENABLE": { + "value": "1" + }, + "PCW_SPI0_SPI0_IO": { + "value": "EMIO" + }, + "PCW_SPI1_GRP_SS1_ENABLE": { + "value": "0" + }, + "PCW_SPI1_GRP_SS2_ENABLE": { + "value": "0" + }, + "PCW_SPI1_PERIPHERAL_ENABLE": { + "value": "1" + }, + "PCW_SPI1_SPI1_IO": { + "value": "MIO 10 .. 15" + }, + "PCW_SPI_PERIPHERAL_FREQMHZ": { + "value": "200" + }, + "PCW_SPI_PERIPHERAL_VALID": { + "value": "1" + }, + "PCW_TTC0_PERIPHERAL_ENABLE": { + "value": "1" + }, + "PCW_TTC0_TTC0_IO": { + "value": "EMIO" + }, + "PCW_TTC_PERIPHERAL_FREQMHZ": { + "value": "50" + }, + "PCW_UART0_GRP_FULL_ENABLE": { + "value": "0" + }, + "PCW_UART0_PERIPHERAL_ENABLE": { + "value": "1" + }, + "PCW_UART0_UART0_IO": { + "value": "MIO 14 .. 15" + }, + "PCW_UART1_GRP_FULL_ENABLE": { + "value": "0" + }, + "PCW_UART1_PERIPHERAL_ENABLE": { + "value": "1" + }, + "PCW_UART1_UART1_IO": { + "value": "MIO 8 .. 9" + }, + "PCW_UART_PERIPHERAL_FREQMHZ": { + "value": "100" + }, + "PCW_UART_PERIPHERAL_VALID": { + "value": "1" + }, + "PCW_UIPARAM_ACT_DDR_FREQ_MHZ": { + "value": "533.333374" + }, + "PCW_UIPARAM_DDR_BUS_WIDTH": { + "value": "16 Bit" + }, + "PCW_UIPARAM_DDR_ECC": { + "value": "Disabled" + }, + "PCW_UIPARAM_DDR_PARTNO": { + "value": "MT41J256M16 RE-125" + }, + "PCW_UIPARAM_GENERATE_SUMMARY": { + "value": "NONE" + }, + "PCW_USB0_PERIPHERAL_ENABLE": { + "value": "1" + }, + "PCW_USB0_RESET_ENABLE": { + "value": "1" + }, + "PCW_USB0_RESET_IO": { + "value": "MIO 48" + }, + "PCW_USB0_USB0_IO": { + "value": "MIO 28 .. 39" + }, + "PCW_USB_RESET_ENABLE": { + "value": "1" + }, + "PCW_USB_RESET_SELECT": { + "value": "Share reset pin" + }, + "PCW_USE_AXI_NONSECURE": { + "value": "0" + }, + "PCW_USE_FABRIC_INTERRUPT": { + "value": "1" + }, + "PCW_USE_S_AXI_GP0": { + "value": "0" + }, + "PCW_USE_S_AXI_HP0": { + "value": "1" + } + }, + "addressing": { + "address_spaces": { + "Data": { + "range": "4G", + "width": "32", + "local_memory_map": { + "name": "Data", + "description": "Address Space Segments", + "address_blocks": { + "address_block": { + "name": "segment1", + "display_name": "segment1", + "base_address": "0x00000000", + "range": "256K", + "width": "18", + "usage": "register" + }, + "address_block": { + "name": "segment2", + "display_name": "segment2", + "base_address": "0x00040000", + "range": "256K", + "width": "19", + "usage": "register" + }, + "address_block": { + "name": "segment3", + "display_name": "segment3", + "base_address": "0x00080000", + "range": "512K", + "width": "20", + "usage": "register" + }, + "address_block": { + "name": "segment4", + "display_name": "segment4", + "base_address": "0x00100000", + "range": "1023M", + "width": "30", + "usage": "register" + }, + "address_block": { + "name": "M_AXI_GP0", + "display_name": "M_AXI_GP0", + "base_address": "0x40000000", + "range": "1G", + "width": "31", + "usage": "register" + }, + "address_block": { + "name": "M_AXI_GP1", + "display_name": "M_AXI_GP1", + "base_address": "0x80000000", + "range": "1G", + "width": "32", + "usage": "register" + }, + "address_block": { + "name": "IO_Peripheral_Registers", + "display_name": "IO Peripheral Registers", + "base_address": "0xE0000000", + "range": "3M", + "width": "32", + "usage": "register" + }, + "address_block": { + "name": "SMC_Memories", + "display_name": "SMC Memories", + "base_address": "0xE1000000", + "range": "80M", + "width": "32", + "usage": "register" + }, + "address_block": { + "name": "SLCR_Registers", + "display_name": "SLCR Registers", + "base_address": "0xF8000000", + "range": "3K", + "width": "32", + "usage": "register" + }, + "address_block": { + "name": "PS_System_Registers", + "display_name": "PS System Registers", + "base_address": "0xF8001000", + "range": "8252K", + "width": "32", + "usage": "register" + }, + "address_block": { + "name": "CPU_Private_Registers", + "display_name": "CPU Private Registers", + "base_address": "0xF8900000", + "range": "6156K", + "width": "32", + "usage": "register" + }, + "address_block": { + "name": "segment5", + "display_name": "segment5", + "base_address": "0xFC000000", + "range": "32M", + "width": "32", + "usage": "register" + }, + "address_block": { + "name": "segment6", + "display_name": "segment6", + "base_address": "0xFFFC0000", + "range": "256K", + "width": "32", + "usage": "register" + } + } + } + } + } + }, + "interface_ports": { + "M_AXI_GP0": { + "mode": "Master", + "address_space_ref": "Data", + "base_address": { + "minimum": "0x40000000", + "maximum": "0x7FFFFFFF", + "width": "32" + } + }, + "S_AXI_HP0": { + "mode": "Slave", + "memory_map_ref": "S_AXI_HP0" + } + }, + "hdl_attributes": { + "BMM_INFO_PROCESSOR": { + "value": "arm > puzzlefw axi_bram_ctrl_0", + "value_src": "default" + }, + "KEEP_HIERARCHY": { + "value": "yes", + "value_src": "default" + } + } + }, + "proc_sys_reset_0": { + "vlnv": "xilinx.com:ip:proc_sys_reset:5.0", + "xci_name": "puzzlefw_proc_sys_reset_0_0", + "xci_path": "ip/puzzlefw_proc_sys_reset_0_0/puzzlefw_proc_sys_reset_0_0.xci", + "inst_hier_path": "proc_sys_reset_0", + "parameters": { + "C_EXT_RST_WIDTH": { + "value": "1" + } + } + }, + "axi_interconnect_0": { + "vlnv": "xilinx.com:ip:axi_interconnect:2.1", + "xci_path": "ip/puzzlefw_axi_interconnect_0_0/puzzlefw_axi_interconnect_0_0.xci", + "inst_hier_path": "axi_interconnect_0", + "xci_name": "puzzlefw_axi_interconnect_0_0", + "parameters": { + "NUM_MI": { + "value": "2" + } + }, + "interface_ports": { + "S00_AXI": { + "mode": "Slave", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0" + }, + "M00_AXI": { + "mode": "Master", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0" + }, + "M01_AXI": { + "mode": "Master", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0" + } + }, + "ports": { + "ACLK": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_RESET": { + "value": "ARESETN" + } + } + }, + "ARESETN": { + "type": "rst", + "direction": "I" + }, + "S00_ACLK": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_BUSIF": { + "value": "S00_AXI" + }, + "ASSOCIATED_RESET": { + "value": "S00_ARESETN" + } + } + }, + "S00_ARESETN": { + "type": "rst", + "direction": "I" + }, + "M00_ACLK": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_BUSIF": { + "value": "M00_AXI" + }, + "ASSOCIATED_RESET": { + "value": "M00_ARESETN" + } + } + }, + "M00_ARESETN": { + "type": "rst", + "direction": "I" + }, + "M01_ACLK": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_BUSIF": { + "value": "M01_AXI" + }, + "ASSOCIATED_RESET": { + "value": "M01_ARESETN" + } + } + }, + "M01_ARESETN": { + "type": "rst", + "direction": "I" + } + }, + "components": { + "xbar": { + "vlnv": "xilinx.com:ip:axi_crossbar:2.1", + "xci_name": "puzzlefw_xbar_0", + "xci_path": "ip/puzzlefw_xbar_0/puzzlefw_xbar_0.xci", + "inst_hier_path": "axi_interconnect_0/xbar", + "parameters": { + "NUM_MI": { + "value": "2" + }, + "NUM_SI": { + "value": "1" + }, + "STRATEGY": { + "value": "0" + } + }, + "interface_ports": { + "S00_AXI": { + "mode": "Slave", + "bridges": [ + "M00_AXI", + "M01_AXI" + ] + } + } + }, + "s00_couplers": { + "interface_ports": { + "M_AXI": { + "mode": "Master", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0" + }, + "S_AXI": { + "mode": "Slave", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0" + } + }, + "ports": { + "M_ACLK": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_BUSIF": { + "value": "M_AXI" + }, + "ASSOCIATED_RESET": { + "value": "M_ARESETN" + } + } + }, + "M_ARESETN": { + "type": "rst", + "direction": "I" + }, + "S_ACLK": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_BUSIF": { + "value": "S_AXI" + }, + "ASSOCIATED_RESET": { + "value": "S_ARESETN" + } + } + }, + "S_ARESETN": { + "type": "rst", + "direction": "I" + } + }, + "components": { + "auto_pc": { + "vlnv": "xilinx.com:ip:axi_protocol_converter:2.1", + "xci_name": "puzzlefw_auto_pc_0", + "xci_path": "ip/puzzlefw_auto_pc_0/puzzlefw_auto_pc_0.xci", + "inst_hier_path": "axi_interconnect_0/s00_couplers/auto_pc", + "parameters": { + "MI_PROTOCOL": { + "value": "AXI4LITE" + }, + "SI_PROTOCOL": { + "value": "AXI3" + } + }, + "interface_ports": { + "S_AXI": { + "mode": "Slave", + "bridges": [ + "M_AXI" + ] + } + } + } + }, + "interface_nets": { + "s00_couplers_to_auto_pc": { + "interface_ports": [ + "S_AXI", + "auto_pc/S_AXI" + ] + }, + "auto_pc_to_s00_couplers": { + "interface_ports": [ + "M_AXI", + "auto_pc/M_AXI" + ] + } + }, + "nets": { + "S_ACLK_1": { + "ports": [ + "S_ACLK", + "auto_pc/aclk" + ] + }, + "S_ARESETN_1": { + "ports": [ + "S_ARESETN", + "auto_pc/aresetn" + ] + } + } + }, + "m00_couplers": { + "interface_ports": { + "M_AXI": { + "mode": "Master", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0" + }, + "S_AXI": { + "mode": "Slave", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0" + } + }, + "ports": { + "M_ACLK": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_BUSIF": { + "value": "M_AXI" + }, + "ASSOCIATED_RESET": { + "value": "M_ARESETN" + } + } + }, + "M_ARESETN": { + "type": "rst", + "direction": "I" + }, + "S_ACLK": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_BUSIF": { + "value": "S_AXI" + }, + "ASSOCIATED_RESET": { + "value": "S_ARESETN" + } + } + }, + "S_ARESETN": { + "type": "rst", + "direction": "I" + } + }, + "interface_nets": { + "m00_couplers_to_m00_couplers": { + "interface_ports": [ + "S_AXI", + "M_AXI" + ] + } + } + }, + "m01_couplers": { + "interface_ports": { + "M_AXI": { + "mode": "Master", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0" + }, + "S_AXI": { + "mode": "Slave", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0" + } + }, + "ports": { + "M_ACLK": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_BUSIF": { + "value": "M_AXI" + }, + "ASSOCIATED_RESET": { + "value": "M_ARESETN" + } + } + }, + "M_ARESETN": { + "type": "rst", + "direction": "I" + }, + "S_ACLK": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_BUSIF": { + "value": "S_AXI" + }, + "ASSOCIATED_RESET": { + "value": "S_ARESETN" + } + } + }, + "S_ARESETN": { + "type": "rst", + "direction": "I" + } + }, + "interface_nets": { + "m01_couplers_to_m01_couplers": { + "interface_ports": [ + "S_AXI", + "M_AXI" + ] + } + } + } + }, + "interface_nets": { + "m00_couplers_to_axi_interconnect_0": { + "interface_ports": [ + "M00_AXI", + "m00_couplers/M_AXI" + ] + }, + "s00_couplers_to_xbar": { + "interface_ports": [ + "s00_couplers/M_AXI", + "xbar/S00_AXI" + ] + }, + "axi_interconnect_0_to_s00_couplers": { + "interface_ports": [ + "S00_AXI", + "s00_couplers/S_AXI" + ] + }, + "xbar_to_m01_couplers": { + "interface_ports": [ + "xbar/M01_AXI", + "m01_couplers/S_AXI" + ] + }, + "m01_couplers_to_axi_interconnect_0": { + "interface_ports": [ + "M01_AXI", + "m01_couplers/M_AXI" + ] + }, + "xbar_to_m00_couplers": { + "interface_ports": [ + "xbar/M00_AXI", + "m00_couplers/S_AXI" + ] + } + }, + "nets": { + "axi_interconnect_0_ACLK_net": { + "ports": [ + "ACLK", + "xbar/aclk", + "s00_couplers/M_ACLK", + "m00_couplers/S_ACLK", + "m01_couplers/S_ACLK" + ] + }, + "axi_interconnect_0_ARESETN_net": { + "ports": [ + "ARESETN", + "xbar/aresetn", + "s00_couplers/M_ARESETN", + "m00_couplers/S_ARESETN", + "m01_couplers/S_ARESETN" + ] + }, + "S00_ACLK_1": { + "ports": [ + "S00_ACLK", + "s00_couplers/S_ACLK" + ] + }, + "S00_ARESETN_1": { + "ports": [ + "S00_ARESETN", + "s00_couplers/S_ARESETN" + ] + }, + "M00_ACLK_1": { + "ports": [ + "M00_ACLK", + "m00_couplers/M_ACLK" + ] + }, + "M00_ARESETN_1": { + "ports": [ + "M00_ARESETN", + "m00_couplers/M_ARESETN" + ] + }, + "M01_ACLK_1": { + "ports": [ + "M01_ACLK", + "m01_couplers/M_ACLK" + ] + }, + "M01_ARESETN_1": { + "ports": [ + "M01_ARESETN", + "m01_couplers/M_ARESETN" + ] + } + } + }, + "axi_apb_bridge_0": { + "vlnv": "xilinx.com:ip:axi_apb_bridge:3.0", + "xci_name": "puzzlefw_axi_apb_bridge_0_0", + "xci_path": "ip/puzzlefw_axi_apb_bridge_0_0/puzzlefw_axi_apb_bridge_0_0.xci", + "inst_hier_path": "axi_apb_bridge_0", + "parameters": { + "C_APB_NUM_SLAVES": { + "value": "1" + }, + "C_DPHASE_TIMEOUT": { + "value": "16" + } + }, + "interface_ports": { + "AXI4_LITE": { + "mode": "Slave", + "bridges": [ + "APB_M" + ] + } + } + }, + "axi_bram_ctrl_0": { + "vlnv": "xilinx.com:ip:axi_bram_ctrl:4.1", + "xci_name": "puzzlefw_axi_bram_ctrl_0_0", + "xci_path": "ip/puzzlefw_axi_bram_ctrl_0_0/puzzlefw_axi_bram_ctrl_0_0.xci", + "inst_hier_path": "axi_bram_ctrl_0", + "parameters": { + "PROTOCOL": { + "value": "AXI4LITE" + }, + "SINGLE_PORT_BRAM": { + "value": "1" + } + }, + "hdl_attributes": { + "BMM_INFO_ADDRESS_SPACE": { + "value": "byte 0x40000000 32 > puzzlefw blk_mem_gen_0", + "value_src": "default" + }, + "KEEP_HIERARCHY": { + "value": "yes", + "value_src": "default" + } + } + }, + "blk_mem_gen_0": { + "vlnv": "xilinx.com:ip:blk_mem_gen:8.4", + "xci_name": "puzzlefw_blk_mem_gen_0_0", + "xci_path": "ip/puzzlefw_blk_mem_gen_0_0/puzzlefw_blk_mem_gen_0_0.xci", + "inst_hier_path": "blk_mem_gen_0" + } + }, + "interface_nets": { + "S_AXI_HP0_0_1": { + "interface_ports": [ + "S_AXI_HP0_0", + "processing_system7_0/S_AXI_HP0" + ] + }, + "axi_bram_ctrl_0_BRAM_PORTA": { + "interface_ports": [ + "axi_bram_ctrl_0/BRAM_PORTA", + "blk_mem_gen_0/BRAM_PORTA" + ] + }, + "axi_interconnect_0_M01_AXI": { + "interface_ports": [ + "axi_bram_ctrl_0/S_AXI", + "axi_interconnect_0/M01_AXI" + ] + }, + "axi_interconnect_0_M00_AXI": { + "interface_ports": [ + "axi_interconnect_0/M00_AXI", + "axi_apb_bridge_0/AXI4_LITE" + ] + }, + "processing_system7_0_DDR": { + "interface_ports": [ + "DDR_0", + "processing_system7_0/DDR" + ] + }, + "processing_system7_0_M_AXI_GP0": { + "interface_ports": [ + "processing_system7_0/M_AXI_GP0", + "axi_interconnect_0/S00_AXI" + ] + }, + "axi_apb_bridge_0_APB_M": { + "interface_ports": [ + "APB_M_0", + "axi_apb_bridge_0/APB_M" + ] + }, + "processing_system7_0_FIXED_IO": { + "interface_ports": [ + "FIXED_IO_0", + "processing_system7_0/FIXED_IO" + ] + } + }, + "nets": { + "processing_system7_0_FCLK_RESET0_N": { + "ports": [ + "processing_system7_0/FCLK_RESET0_N", + "proc_sys_reset_0/ext_reset_in" + ] + }, + "proc_sys_reset_0_peripheral_aresetn": { + "ports": [ + "proc_sys_reset_0/peripheral_aresetn", + "axi_interconnect_0/S00_ARESETN", + "axi_interconnect_0/M00_ARESETN", + "axi_apb_bridge_0/s_axi_aresetn", + "axi_bram_ctrl_0/s_axi_aresetn", + "axi_interconnect_0/M01_ARESETN" + ] + }, + "proc_sys_reset_0_interconnect_aresetn": { + "ports": [ + "proc_sys_reset_0/interconnect_aresetn", + "axi_interconnect_0/ARESETN" + ] + }, + "IRQ_F2P_1": { + "ports": [ + "IRQ_F2P", + "processing_system7_0/IRQ_F2P" + ] + }, + "proc_sys_reset_0_peripheral_reset": { + "ports": [ + "proc_sys_reset_0/peripheral_reset", + "peripheral_reset_0" + ] + }, + "sys_clk_1": { + "ports": [ + "sys_clk", + "proc_sys_reset_0/slowest_sync_clk", + "processing_system7_0/M_AXI_GP0_ACLK", + "processing_system7_0/S_AXI_HP0_ACLK", + "axi_interconnect_0/ACLK", + "axi_interconnect_0/S00_ACLK", + "axi_interconnect_0/M00_ACLK", + "axi_apb_bridge_0/s_axi_aclk", + "axi_bram_ctrl_0/s_axi_aclk", + "axi_interconnect_0/M01_ACLK" + ] + }, + "processing_system7_0_FCLK_CLK0": { + "ports": [ + "processing_system7_0/FCLK_CLK0", + "ps_fclk" + ] + } + }, + "addressing": { + "/": { + "address_spaces": { + "S_AXI_HP0_0": { + "range": "4G", + "width": "32", + "segments": { + "SEG_processing_system7_0_HP0_DDR_LOWOCM": { + "address_block": "/processing_system7_0/S_AXI_HP0/HP0_DDR_LOWOCM", + "offset": "0x00000000", + "range": "512M" + } + } + } + }, + "memory_maps": { + "APB_M_0": { + "address_blocks": { + "Reg": { + "base_address": "0", + "range": "64K", + "width": "16", + "usage": "register" + } + } + } + } + }, + "/processing_system7_0": { + "address_spaces": { + "Data": { + "segments": { + "SEG_APB_M_0_Reg": { + "address_block": "/APB_M_0/Reg", + "offset": "0x43000000", + "range": "2M" + }, + "SEG_axi_bram_ctrl_0_Mem0": { + "address_block": "/axi_bram_ctrl_0/S_AXI/Mem0", + "offset": "0x40000000", + "range": "8K" + } + } + } + } + } + } + } +} \ No newline at end of file diff --git a/fpga/vivado/redpitaya_puzzlefw.xpr b/fpga/vivado/redpitaya_puzzlefw.xpr new file mode 100644 index 0000000..4fe72d7 --- /dev/null +++ b/fpga/vivado/redpitaya_puzzlefw.xpr @@ -0,0 +1,522 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Vivado Synthesis Defaults + + + + + + + + + + + + Vivado Synthesis Defaults + + + + + + + + + + + + Vivado Synthesis Defaults + + + + + + + + + + + + Vivado Synthesis Defaults + + + + + + + + + + + + Vivado Synthesis Defaults + + + + + + + + + + + + Vivado Synthesis Defaults + + + + + + + + + + + + Vivado Synthesis Defaults + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Default settings for Implementation. + + + + + + + + + + + + + + + + + + + Default settings for Implementation. + + + + + + + + + + + + + + + + + + + Default settings for Implementation. + + + + + + + + + + + + + + + + + + + Default settings for Implementation. + + + + + + + + + + + + + + + + + + + Default settings for Implementation. + + + + + + + + + + + + + + + + + + + Default settings for Implementation. + + + + + + + + + + + + + + + + + + + Default settings for Implementation. + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + default_dashboard + + +