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redpitaya-puzzlefw
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Reset FPGA via GPIO during boot

This commit is contained in:
Joris van Rantwijk 2024-10-05 00:34:40 +02:00
parent d2b39354c8
commit 9a9163b7f0
2 changed files with 19 additions and 0 deletions
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11
sw/buildroot_overlay/etc/init.d/S90program_fpga.sh
View File

@ -30,6 +30,13 @@ start() {
exit 1 exit 1
fi fi
# Drive internal GPIO line 0 low to reset FPGA.
# Note: EMIO GPIO line n is gpio (n + 54) in Linux.
gpioset 0 54=0
# Drive internal GPIO line 2 high to enable ADC duty cycle stabilizer.
gpioset 0 56=0
# Program FPGA. # Program FPGA.
echo "Programming FPGA ..." echo "Programming FPGA ..."
echo 0 > /sys/class/fpga_manager/fpga0/flags echo 0 > /sys/class/fpga_manager/fpga0/flags
@ -37,6 +44,10 @@ start() {
# Wait until FPGA programmed. # Wait until FPGA programmed.
sleep 5 sleep 5
# Drive internal GPIO line 0 high to release FPGA reset.
gpioset 0 54=1
sleep 1
} }
case "$1" in case "$1" in

8
sw/buildroot_overlay/etc/init.d/S91puzzlefw_driver.sh
View File

@ -14,6 +14,14 @@ start() {
exit 1 exit 1
fi fi
# Check that the FPGA has finished reset.
# If the FPGA is in reset, loading the driver will crash the system.
reset_done="$(gpioget 0 55)"
if [ "$reset_done" -ne 1 ]; then
echo "ERROR: FPGA in reset" >&2
exit 1
fi
# Load module. # Load module.
echo "Loading puzzlefw driver ..." echo "Loading puzzlefw driver ..."
insmod /opt/puzzlefw/driver/puzzlefw.ko insmod /opt/puzzlefw/driver/puzzlefw.ko