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redpitaya-puzzlefw
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Drive unused output ports

This commit is contained in:
Joris van Rantwijk 2024-08-28 00:58:27 +02:00
parent 209da7065a
commit 8ccfff2264
1 changed files with 20 additions and 1 deletions
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21
fpga/rtl/puzzlefw_top.vhd
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@ -163,12 +163,31 @@ architecture arch of puzzlefw_top is
begin begin
-- Drive LEDs.
led_o(0) <= r_adcclk_led; -- blinking LED, 1 Hz led_o(0) <= r_adcclk_led; -- blinking LED, 1 Hz
led_o(1) <= s_reg_control.acquisition_en; -- acquisition enabled led_o(1) <= s_reg_control.acquisition_en; -- acquisition enabled
led_o(2) <= s_reg_status.trig_waiting; -- waiting for trigger led_o(2) <= s_reg_status.trig_waiting; -- waiting for trigger
-- led_o(3) <= timetagger_en -- TODO: led_o(3) <= timetagger_en
led_o(7 downto 4) <= s_reg_control.led_state(7 downto 4); led_o(7 downto 4) <= s_reg_control.led_state(7 downto 4);
-- Enable ADC clock duty cycle stabilizer.
adc_cdcs_o <= '1';
-- ADC clock outputs are not connected on vanilla Red Pitaya 125-14.
adc_clk_o <= (others => 'Z');
-- Drive safe levels to unused DAC pins.
dac_dat_o <= (others => '0');
dac_wrt_o <= '0';
dac_sel_o <= '0';
dac_clk_o <= '0';
dac_rst_o <= '0';
dac_pwm_o <= (others => 'Z');
-- Use extension I/O pins as inputs.
exp_p_io <= (others => 'Z');
exp_n_io <= (others => 'Z');
-- Differential clock input for ADC clock. -- Differential clock input for ADC clock.
inst_ibuf_adc_clk: IBUFDS inst_ibuf_adc_clk: IBUFDS
port map ( port map (