From 8ccfff22642684365f399719f16fc63006aac24b Mon Sep 17 00:00:00 2001 From: Joris van Rantwijk Date: Wed, 28 Aug 2024 00:58:27 +0200 Subject: [PATCH] Drive unused output ports --- fpga/rtl/puzzlefw_top.vhd | 21 ++++++++++++++++++++- 1 file changed, 20 insertions(+), 1 deletion(-) diff --git a/fpga/rtl/puzzlefw_top.vhd b/fpga/rtl/puzzlefw_top.vhd index 8b2d105..fad74b1 100644 --- a/fpga/rtl/puzzlefw_top.vhd +++ b/fpga/rtl/puzzlefw_top.vhd @@ -163,12 +163,31 @@ architecture arch of puzzlefw_top is begin + -- Drive LEDs. led_o(0) <= r_adcclk_led; -- blinking LED, 1 Hz led_o(1) <= s_reg_control.acquisition_en; -- acquisition enabled led_o(2) <= s_reg_status.trig_waiting; -- waiting for trigger - -- led_o(3) <= timetagger_en + -- TODO: led_o(3) <= timetagger_en led_o(7 downto 4) <= s_reg_control.led_state(7 downto 4); + -- Enable ADC clock duty cycle stabilizer. + adc_cdcs_o <= '1'; + + -- ADC clock outputs are not connected on vanilla Red Pitaya 125-14. + adc_clk_o <= (others => 'Z'); + + -- Drive safe levels to unused DAC pins. + dac_dat_o <= (others => '0'); + dac_wrt_o <= '0'; + dac_sel_o <= '0'; + dac_clk_o <= '0'; + dac_rst_o <= '0'; + dac_pwm_o <= (others => 'Z'); + + -- Use extension I/O pins as inputs. + exp_p_io <= (others => 'Z'); + exp_n_io <= (others => 'Z'); + -- Differential clock input for ADC clock. inst_ibuf_adc_clk: IBUFDS port map (