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redpitaya-puzzlefw
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Remove digital debug output signals

This commit is contained in:
Joris van Rantwijk 2024-08-31 13:17:22 +02:00
parent eb1cd6219f
commit 8562c9346d
1 changed files with 1 additions and 37 deletions
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38
fpga/rtl/puzzlefw_top.vhd
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@ -166,13 +166,6 @@ architecture arch of puzzlefw_top is
signal s_dig_deglitch: std_logic_vector(3 downto 0);
signal s_dig_sample: std_logic_vector(3 downto 0);
-- TODO
signal r_mhz_cnt: unsigned(7 downto 0);
signal r_khz_cnt: unsigned(9 downto 0);
signal r_blink_mhz: std_logic;
signal r_blink_mhz_d: std_logic;
signal r_blink_khz: std_logic;
begin
-- Drive LEDs.
@ -197,38 +190,9 @@ begin
dac_pwm_o <= (others => 'Z');
-- Use extension I/O pins as inputs only.
-- TODO -- temporary test pulse generator
exp_p_io <= (2 => r_blink_khz, 3 => r_blink_khz, 4 => r_blink_mhz, 5 => r_blink_mhz, 6 => r_blink_mhz_d, 7 => r_blink_mhz_d, others => 'Z');
exp_p_io <= (others => 'Z');
exp_n_io <= (others => 'Z');
-- TODO
process (clk_adc) is
begin
if rising_edge(clk_adc) then
if r_mhz_cnt < 124 then
r_mhz_cnt <= r_mhz_cnt + 1;
else
r_mhz_cnt <= (others => '0');
if r_khz_cnt < 999 then
r_khz_cnt <= r_khz_cnt + 1;
else
r_khz_cnt <= (others => '0');
end if;
end if;
if r_mhz_cnt < 62 then
r_blink_mhz <= '0';
else
r_blink_mhz <= '1';
end if;
r_blink_mhz_d <= r_blink_mhz;
if r_khz_cnt < 500 then
r_blink_khz <= '0';
else
r_blink_khz <= '1';
end if;
end if;
end process;
-- Differential clock input for ADC clock.
inst_ibuf_adc_clk: IBUFDS
port map (