Add development manual
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@ -28,7 +28,7 @@ PuzzleFW has the following features:
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Further details about the firmware are in these documents:
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- [User manual](doc/user_manual.md)
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- Developer manual, including the build procedure, to be written
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- [Developer manual](doc/devel_manual.md), including build procedure
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- [FPGA firmware description](doc/fpga_firmware.md)
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## Supported boards
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@ -0,0 +1,479 @@
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---
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gitea: none
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include_toc: true
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---
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# Development manual
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This document gives an overview of the internal structure of the PuzzleFW firmware package.
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It also describes the process to build the FPGA firmware and the embedded software.
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## FPGA design overview
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The FPGA captures ADC samples and digital input signals.
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ADC samples go into the analog acquisition chain.
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The acquisition chain handles triggering and optional downsampling.
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A configurable number of samples are collected following each trigger event.
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Trigger events and collected samples are transferred to a buffer in DDR memory via the AXI slave interface of the Zynq processing system.
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Digital signals go into a timetagger subsystem.
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The timetagger detects edges on selected signals and assigns timestamps to such events.
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Timestamped events are transferred to a buffer in DDR memory via the AXI slave interface.
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All synchronous elements are clocked at 125 MHz, derived from the ADC sample clock.
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### Block design
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A Vivado block design contains the Zynq processing system (ARM), AXI interconnect, and AXI-to-APB bridge.
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This block design is instantiated in the top-level VHDL file.
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### PS-to-PL interfaces
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The following interfaces are used between the PS (ARM) and PL (FPGA):
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- M\_AXI\_GP0 <br>
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Used by embedded software to read and write registers in the FPGA via AXI and APB bus.
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This interface is mapped to addresses 0x43000000 to 0x431fffff in the PS address map.
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- S\_AXI\_HP0 <br>
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Used by FPGA firmware to read and write DDR memory.
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- GPIO <br>
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The PS controls a few specific digital signals in the FPGA via GPIO lines.
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One of these lines is a global reset signal for the FPGA firmware.
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- SPI0 <br>
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Routed via EMIO through the FPGA to the SPI bus of the ADCs (only on 4-input boards).
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- IRQ\_F2P <br>
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Used by FPGA firmware to trigger interrupts in the PS.
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- FCLK\_CLK0 <br>
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Fixed 200 MHz clock generated by the PS.
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On 4-input boards, the FPGA uses this clock as reference for IODELAY primitives.
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On 2-input boards, this clock is not used.
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### ADC input timing
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The ADC transfers samples via a parallel source-synchronous interface.
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The interface is synchronous to a 125 MHz clock output signal from the ADC.
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This is also the main clock source of the FPGA design.
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On 2-input Red Pitaya boards, the ADC is hardwired to operate in _full rate CMOS mode_.
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Each analog channel has 14 parallel data signals from ADC to FPGA.
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These data signals transition on the falling clock edge and are captured by the FPGA on the rising clock edge.
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Data signals are captured in the FPGA in IOB flip-flops.
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These flip-flops are clocked on a 125 MHz clock, derived by a PLL from the ADC output clock.
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It turns out that a phase shift of 90 degrees in the PLL provides near-optimal timing for capturing the data signals.
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This follows from synthesizer timing reports and has been confirmed experimentally by testing different PLL phase shift settings.
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On 4-input Red Pitaya boards, only 7 parallel data signals per analog channel are connected from the ADCs to the FPGA.
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The ADCs must be programmed (via SPI) to operate in _double data rate CMOS mode_.
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In this mode, the data lines transition on both edges of the 125 MHz clock.
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The data signals are routed through IDELAY components in the FPGA before being captured in IDDR registers.
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The IDDR are clocked on the 125 MHz clock from the ADC that produces the samples (without PLL).
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The IDELAY components use a fixed delay, tuned to 2.34 ns to optimize data capture timing.
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Timing reports indicate that this provides sufficient margin.
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This has been confirmed experimentally by testing different phase-shift settings of the ADC output clock.
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The main FPGA design runs on a 125 MHz clock, derived by a PLL from the ADC that samples channels 1 and 2.
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Transferring samples from channels 3 and 4 to the main clock is slightly tricky because the two ADC clocks may be skewed with respect to each other.
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A few mysterious timing constraints were added to deal with this.
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## Embedded software overview
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The purpose of the embedded software is to make the system remotely accessible via the network.
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The software collects data from the FPGA and transmits it via TCP.
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Similarly, the software accepts remote control commands via TCP and executes these by accessing registers in the FPGA.
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### Operating system
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The embedded software runs within an embedded Linux system on the Red Pitaya.
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The core operating system is based on [Buildroot](https://buildroot.org/), a framework that builds an embedded Linux system from scratch.
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Buildroot automatically downloads and builds many additional open source packages that are needed to construct the embedded system.
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Among these packages is a cross-compilation toolchain.
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The kernel for the embedded system is built from the [Xilinx distribution of the Linux kernel](https://github.com/Xilinx/linux-xlnx).
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It is necessary to use the Xilinx variant of Linux.
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The vanilla Linux kernel can run on the Red Pitaya, but the Xilinx kernel provides important features that are missing from the vanilla kernel, such as programming the FPGA.
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The shell and system utilities of the embedded system are based on Busybox.
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Dropbear is installed as SSH server, but disabled by default.
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The set of packages to be installed in the embedded system, along with their compile-time settings, are specified in the Buildroot configuration.
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Further tweaking of the embedded system is done via a _filesystem overlay_: a set of files that are injected into the embedded root filesystem as a final step.
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The overlay mechanism is used to install boot scripts and configuration files.
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It is also used to install custom user space software.
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### Boot flow
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[U-Boot](https://source.denx.de/u-boot/u-boot) is used as boot loader and as _secondary program loader_ (SPL).
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Building U-Boot requires a proper device tree for the board.
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Building the U-Boot SPL image also requires the file `ps7_init_gpl.c`.
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The contents of this file depend on the configuration of the Zynq programming system which is specified in the Vivado block design.
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To generate this file, the FPGA design must be _exported_ from Vivado in the form of an XSA file.
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The XSA file is actually a ZIP archive which contains `ps7_init_gpl.c` and the corresponding header file.
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The U-Boot build script (`12_build_uboot.sh`) copies these files to the correct location in the U-Boot source tree.
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The boot process of the Red Pitaya is as follows:
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- The Zynq PS boots from ROM.
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The ROM program reads `boot.bin` from the SD card and runs it.
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- `boot.bin` is the U-Boot SPL image.
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It initializes many subsystems in the Zynq PS, including the DDR memory controller.
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It then reads `u-boot.img` from the SD card and runs it.
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Note that we don't use a Xilinx FSBL at all.
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Many Zynq tutorials explain how to build `boot.bin` using Xilinx tools.
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That requires a non-free FSBL image which must be built in a Vitis project.
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The PuzzleFW package avoids that whole mess by using U-Boot SPL instead.
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- `u-boot.img` is the main U-Boot program image.
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It reads and executes `boot.scr`, a script which describes the Linux boot process.
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The script instructs U-Boot to read the Linux kernel `uImage`,
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the device tree `devicetree.dtb` and the root filesystem image `rootfs.cpio.uboot`
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from the SD card.
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It then runs the Linux kernel.
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- `uImage` is the Linux kernel image.
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The kernel initializes drivers and subsystems.
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The root filesystem is unpacked and mounted as a RAM filesystem.
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The filesystem is writeable, but any changes remain in RAM and will be forgotten on the next reboot.
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- A set of boot scripts are invoked to initialize the embedded system and start services.
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Most of these scripts are prepared by Buildroot, but some scripts have been tweaked or specially created for PuzzleFW.
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These scripts take care of the following:
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- Read the MAC address from the EEPROM on the Red Pitaya board, and assign it to the Ethernet interface.
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- Set a unique hostname `rp-XXXXXX` based on the MAC address.
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- Obtain an IPv4 address via DHCP or a preconfigured static address.
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This is controlled by a file in the configuration partition of the SD card.
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- Start an SSH server, if enabled. By default, this is disabled.
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- Read a BIT file from the SD card and program the FPGA.
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Information in the EEPROM is used to determine which FPGA image must be used.
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- Configure ADCs on the Red Pitaya board via SPI or GPIO.
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- Load the Linux kernel driver to access the FPGA firmware.
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- Run a user space program that accepts remote control commands via TCP.
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### Linux kernel driver
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A custom Linux kernel module is used to access the FPGA firmware.
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This module is called `puzzlefw.ko`.
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The driver is based on the Linux UIO framework.
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The kernel module itself has minimal functionality.
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Its only functions are:
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- mapping the register address range of the FPGA to user space via mmap
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- mapping the DMA buffer to user space via mmap
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- handling FPGA interrupts and notifying user space via UIO
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All non-trivial interactions with the FPGA are done in user space.
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This includes managing the DMA data flow.
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### User space software
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The FPGA firmware is controlled by a user space program.
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This program accepts remote control commands via TCP.
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Commands are handled by reading and writing registers in the FPGA.
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The program also collects data from the FPGA via DMA, and transmits these data through the network via TCP.
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The program is written in C++.
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It uses Boost Asio, an asynchronous I/O framework.
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### Configuration partition
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While the embedded software runs, the root filesystem is located in RAM.
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The filesystem is writable, but any changes will be lost on the next boot.
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In order to store persistent settings, the SD card has a separate configuration partition.
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This is `/dev/mmcblk0p2`, formatted as Ext4.
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The following files are stored there:
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- `network.conf`: IP address configuraton (DHCP or static IP address)
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- `calibration.conf`: analog calibration coefficients
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- `start_ssh.conf`: enables or disables starting the SSH server
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- SSH host key
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The configuration partition is temporarily mounted read-only during boot, to read the configuration files.
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Otherwise, the partition is only accessed when the configuration is modified.
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In such cases, the partition is temporarily mounted to write the updated files, then unmounted again.
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As a result, writes to the SD card occur only when the user changes the persistent configuration of the system.
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This avoids unnecessary wear of the SD card.
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## Build procedure
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A Linux PC (x86-64) is required to build the system.
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Development was done with Debian 12 (bookworm).
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Other Linux distributions will probably also work.
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The build process consists of two main steps.
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These steps must be done in the following order:
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1. Build the FPGA firmware for the Zynq PL.
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2. Build the embedded software for the Zynq PS.
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## Building FPGA firmware
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Building the FPGA firmware requires Vivado release 2020.2.
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Later releases will probably work, but may require adjustments.
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There are two ways to build the firmware: as a Vivado project, or in Vivado non-project mode.
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In most cases, non-project mode will be easier.
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### Preparing the build environment
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**Install Vivado** <br>
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Download and install Vivado 2020.2.
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The build scripts assume that Vivado is installed in `/opt/Xilinx/Vivado/2020.2`.
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If a different location is used, it must be configured in the script environment file.
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**Configure paths** <br>
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If necessary, edit the file `redpitaya-puzzlefw/fpga/script_env` and make sure that `VIVADO_DIR` points to the directory where Vivado is installed.
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**Install board files** <br>
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When running Vivado in project mode, it requires board definition files
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for the Red Pitaya.
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These files are available from the original Red Pitaya FPGA repository.
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Use the following steps to download and install these files.
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- Go to directory `redpitaya-puzzlefw/fpga`
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- Run `./01_get_redpitaya.sh`
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- Copy the complete folder `redpitaya-puzzlefw/fpga/RedPitaya-FPGA/brd/redpitaya`
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to `/opt/Xilinx/Vivado/2020.2/data/boards/board_files`
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### Building FPGA firmware in non-project mode
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There are two top-level designs, each targeting a specific Red Pitaya board type.
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These designs are built in separate design runs:
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- `puzzlefw_top` for the normal (2-input) Red Pitaya
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- `puzzlefw_top_4ch` for the 4-input Red Pitaya
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The following steps invoke Vivado in non-project mode to handle synthesis, implementation and bitfile generation of each top-level design.
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- Go to directory `redpitaya-puzzlefw/fpga`
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- Run `./11_build_bitfile.sh`
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- Run `./12_build_bitfile_4ch.sh`
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It is normal for the build process to display a large number of messages and warnings.
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The build process produces the following output files:
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- `puzzlefw_top.bit.bin` <br>
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This file is required to program the FPGA.
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- `redpitaya_puzzlefw.xsa` <br>
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This file contains a description of the system configuration.
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It is necessary to build U-boot.
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- Similar files for the 4-input design.
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The build process also creates various logs and report files in directory `vivado/output` (or `output_4ch`).
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It is recommended to review the contents of `vivado/output/post_route_timing.rpt` to make sure that it does not report any timing violations and contains the line `All user specified timing constraints are met`.
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### Building FPGA firmware in project mode
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The repository contains a Vivado project file to build the design for the normal (2-input) Red Pitaya.
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There is currently no project file for the 4-input board.
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The following steps may be used to build the design in Vivado in project mode:
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- Start Vivado, typically by running something like <br>
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`source /opt/Xilinx/Vivado/2020.1/settings64.sh ; vivado`
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- Open the project file `redpitaya-puzzlefw/fpga/vivado/redpitaya_puzzlefw.xpr`.
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- In the *Flow Navigator* panel on the left, click on "Run Synthesis", then click "Ok".
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It may appear that very little is happening, but synthesis should be running in the background.
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The status is displayed in the *Design Runs* panel at the bottom of the screen.
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- When synthesis completes successfully, choose "Run Implementation" and click "Ok".
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- When implementation completes successfully, choose "Generate Bitstream" and click "Ok".
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- When bitstream generation completes successfully, choose "View Reports".
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- In the *Project Summary* panel, check that timing is ok (Number of Falling Endpoints should be 0).
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- In the main menu bar, click *File*, *Export*, *Export Hardware*.
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Select "Pre-synthesis".
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Change XSA file name and export folder to write the XSA file to
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`redpitaya-puzzlefw/fpga/redpitaya_puzzlefw.xsa`.
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Then click "Finish".
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The build process produces a BIT file `puzzlefw_top.bit` containing the FPGA design.
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The Zynq software needs this file in a different format (`.bit.bin`) which can not be created by the Vivado IDE.
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Use the following steps to convert the BIT file:
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- Go to directory `redpitaya-puzzlefw/fpga`
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- Run `./make_binfile.sh vivado/redpitaya_puzzlefw.runs/impl_1/puzzlefw_top.bit`
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### Editing the block design
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Most source files for the FPGA firmware can be edited with any text editor.
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The VHDL source files are in directory `redpitaya-puzzlefw/fpga/rtl`.
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Constraint files are in `redpitaya-puzzlefw/fpga/constraints`.
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The only exception is the block design that links the Zynq processing system to the FPGA logic.
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The block design is stored as `redpitaya-puzzlefw/fpga/vivado/redpitaya_puzzlefw.srcs/sources_1/bd/puzzlefw/puzzlefw.bd`.
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This file can only be edited through Vivado, as follows:
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- Start Vivado as described above.
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- Open the project file `redpitaya-puzzlefw/fpga/vivado/redpitaya_puzzlefw.xpr`.
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- In the *Flow Navigator* panel on the left, click on "Open Block Design".
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- Make changes as needed.
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- In the main menu bar, click *File*, *Save Block Design*.
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Both top-level designs (2-input and 4-input boards) use the same block design file.
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This is a tricky situation because the block design file targets a specific FPGA part (e.g. `xc7z010clg400-1`), but the two boards have different FPGA parts.
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When using the non-project build flow, we find that this just seems to work without issues.
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During the build flow, Vivado quietly modifies the block design file to match the target part of the design run.
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### Adding VHDL files to the project
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When VHDL files are added to the project, both the Vivado project and the non-project build script must be updated.
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To update the Vivado project:
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- Open the project file `redpitaya-puzzlefw/fpga/vivado/redpitaya_puzzlefw.xpr`.
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- In the *Flow Navigator* panel on the left, click "Add Sources".
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- Add VHDL files directly from the directory `redpitaya-puzzlefw/fpga/rtl`.
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Do not select "Copy sources into project".
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- Vivado may get a confused because, by default, it does not support VHDL-2008.
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To fix this, in the *Sources* panel, click "Libraries" below the hierachy tree.
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Right-click each new VHDL file, choose "Set File Type" and change the file type to "VHDL 2008".
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Vivado stores all project settings in the XPR file.
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Changes to that file must be tracked in the Git repository.
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To update the non-project build script:
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- Open `redpitaya-puzzlefw/fpga/vivado/nonproject.tcl` in a text editor.
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- Add `read_vhdl` statements to load the new VHDL files.
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## Building embedded software
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### Preparing the build environment
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Install the following Debian packages (or equivalent packages on other Linux distributions):
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<br>
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`build-essential`,
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`bc`,
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`bzip2`,
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`cpio`,
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`dosfstools`,
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`file`,
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`git`,
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`libncurses-dev`,
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`mtools`,
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`patch`,
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`perl`,
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`rsync`,
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`unzip`,
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`wget`.
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### Downloading software
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Use the following steps to download required software packages:
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- Go to directory `redpitaya-puzzlefw/sw`
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- Run `./01_get_buildroot.sh` to download [Buildroot](https://buildroot.org).
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- Run `./02_get_uboot.sh` to download [U-Boot](https://source.denx.de/u-boot/u-boot).
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- Run `./03_get_kernel.sh` to download the [Xilinx distribution of the Linux kernel](https://github.com/Xilinx/linux-xlnx).
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### Building embedded software
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Use the following steps to build the embedded software:
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- Go to directory `redpitaya-puzzlefw/sw`
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- Run `./11_build_buildroot.sh` to configure and build Buildroot.
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<br>
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One of the outcomes of this step is a cross-compilation toolchain for the ARM architecture.
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Other build steps need this toolchain, therefore this must be the first step of the build flow.
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- Run `./12_build_uboot.sh` to configure and build U-Boot.
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<br>
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This step requires the file `redpitaya-puzzlefw/fpga/redpitaya_puzzlefw.xsa` from the FPGA build flow.
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- Run `./13_build_kernel.sh` to configure and build the Linux kernel.
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- Run `./14_build_devicetree.sh` to build the device tree.
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- Run `./15_build_driver.sh` to build the Linux kernel module that provides access to the FPGA firmware.
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- Run `./16_build_userspace.sh` to build user space applications that will run on the Red Pitaya.
|
||||
- Run `./21_rebuild_rootfs.sh` to re-build the embedded root filesystem, including the kernel driver and user space tools that were built during previous steps.
|
||||
- Run `./22_prepare_sdcard.sh` to collect the files that must be installed on the SD card for the Red Pitaya.
|
||||
- Run `./23_sdcard_image.sh` to build an image file which can be written to the SD card.
|
||||
|
||||
### Changing the Buildroot configuration
|
||||
|
||||
The Buildroot configuration for this project is stored in the folder `config`.
|
||||
To change the configuration, start by applying the existing settings, then run the Buildroot configuration tool, then copy the new settings to the `config` folder.
|
||||
Use the following steps:
|
||||
|
||||
- Copy `sw/config/buildroot_puzzlefw_defconfig` to `sw/buildroot-2023.02.08/.config`
|
||||
- Go to `sw/buildroot-2023.02.8`
|
||||
- Run `make olddefconfig`
|
||||
- Run `make nconfig`
|
||||
- Use the menu to change the configuration as needed.
|
||||
- Run `make savedefconfig`
|
||||
- Copy `sw/buildroot-2023.02.08/defconfig` to `sw/config/buildroot_puzzlefw_defconfig`
|
||||
|
||||
After changing the Buildroot configuration, rerun step `11_build_buildroot.sh`.
|
||||
|
||||
### Changing the U-Boot configuration
|
||||
|
||||
The U-Boot configuration for this project is stored in the folder `config`.
|
||||
To change the configuration, start by applying the existing settings, then run the U-boot configuration tool, then copy the new settings to the `config` folder.
|
||||
Use the following steps:
|
||||
|
||||
- Copy `sw/config/uboot_redpitaya_puzzlefw_defconfig` to `sw/u-boot/configs/redpitaya_puzzlefw_defconfig`
|
||||
- Go to `sw/u-boot`
|
||||
- Run `make redpitaya_puzzlefw_defconfig`
|
||||
- Run `make nconfig`
|
||||
- Use the menu to change the configuration as needed.
|
||||
- Run `make savedefconfig`
|
||||
- Copy `sw/u-boot/defconfig` to `sw/config/uboot_redpitaya_puzzlefw_defconfig`
|
||||
|
||||
After changing the Buildroot configuration, rerun step `12_build_uboot.sh`.
|
||||
|
||||
### Changing the Linux kernel configuration
|
||||
|
||||
The Linux kernel configuration for this project is stored in the folder `config`.
|
||||
To change the configuration, start by applying the existing settings, then run the kernel configuration tool, then copy the new settings to the `config` folder.
|
||||
Use the following steps:
|
||||
|
||||
- Copy `sw/config/linux_redpitaya_puzzlefw_defconfig` to `sw/linux-xlnx/.config`
|
||||
- Go to `sw/linux-xlnx`
|
||||
- Run `make ARCH=arm olddefconfig`
|
||||
- Run `make ARCH=arm nconfig`
|
||||
- Use the menu to change the configuration as needed.
|
||||
- Run `make ARCH=arm savedefconfig`
|
||||
- Copy `sw/linux-xlnx/defconfig` to `sw/config/linux_redpitaya_puzzlefw_defconfig`
|
||||
|
||||
After changing the Buildroot configuration, rerun step `13_build_kernel.sh`.
|
||||
|
||||
### Preparing the SD card
|
||||
|
||||
This section explains how to set up the SD card manually.
|
||||
It is not normally necessary to do this.
|
||||
An easier way to set up the SD card is by building an image file and writing it to the card.
|
||||
|
||||
The SD card contains two partitions:
|
||||
|
||||
- `/dev/mmcblk0p1` is a 256 MB partition with FAT filesystem
|
||||
- `/dev/mmcblk0p2` is a 256 MB partition with an Ext4 filesystem
|
||||
|
||||
The FAT partition contains the following files:
|
||||
|
||||
| File | Description |
|
||||
|----------------------------|-------------|
|
||||
| `boot.bin` | first stage boot loader for the Zynq (built by U-Boot) |
|
||||
| `u-boot.img` | main boot loader program (U-Boot) |
|
||||
| `boot.scr` | boot script for U-Boot |
|
||||
| `devicetree.dtb` | device tree for the Linux kernel |
|
||||
| `uImage` | Linux kernel image |
|
||||
| `rootfs.cpio.uboot` | root filesystem image |
|
||||
| `puzzlefw_top.bit.bin` | FPGA firmware image for 2-input board |
|
||||
| `puzzlefw_top_4ch.bit.bin` | FPGA firmware image for 4-input board |
|
||||
|
||||
The Ext4 partition can be left empty initially.
|
||||
Configuration files will be written to this partition by the embedded system.
|
||||
|
||||
The following commands may be used to format the two partitions:
|
||||
|
||||
mkdosfs -F 16 /dev/mmcblk0p1
|
||||
mke2fs -t ext4 -b 4096 /dev/mmcblk0p2
|
||||
|
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|
After Width: | Height: | Size: 22 KiB |
|
|
@ -278,7 +278,7 @@ analog acquisition chain and the timetagger as described in the
|
|||
Clients may connect to TCP port 5025 to send commands.
|
||||
Multiple clients may be simultaneously connected to this port.
|
||||
In that case, it is the responsibility of the clients to make sure
|
||||
that they do not interfere with eachother.
|
||||
that they do not interfere with each other.
|
||||
|
||||
The remote control protocol is based on ASCII strings.
|
||||
The protocol is vaguely similar to SCPI, but it is not compatible with SCPI.
|
||||
|
|
@ -303,7 +303,7 @@ to indicate that the command was completed successfully,
|
|||
or by sending an error message.
|
||||
|
||||
Some commands require one or more _parameters_.
|
||||
In the command string, the command and parameters are separated from eachother by space characters.
|
||||
In the command string, the command and parameters are separated from each other by space characters.
|
||||
|
||||
The response to some queries may consist of multiple data elements.
|
||||
In the response string, such data elements are separated by space characters.
|
||||
|
|
|
|||
Loading…
Reference in New Issue