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redpitaya-puzzlefw
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Move trigger inputs to exp_p_io[0 .. 3] 

These inputs are also accessible through the logic analyzer module.
This commit is contained in:
Joris van Rantwijk 2024-10-10 22:02:44 +02:00
parent b445abd149
commit 4814275863
5 changed files with 9 additions and 16 deletions
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6
fpga/constraints/red_pitaya.xdc
View File

@ -171,9 +171,9 @@ set_property PACKAGE_PIN M15 [get_ports {exp_n_io[7]}]
# Pull down digital inputs. # Pull down digital inputs.
set_property PULLDOWN TRUE [get_ports {exp_p_io[0]}] set_property PULLDOWN TRUE [get_ports {exp_p_io[0]}]
set_property PULLDOWN TRUE [get_ports {exp_n_io[0]}]
set_property PULLDOWN TRUE [get_ports {exp_p_io[1]}] set_property PULLDOWN TRUE [get_ports {exp_p_io[1]}]
set_property PULLDOWN TRUE [get_ports {exp_n_io[1]}] set_property PULLDOWN TRUE [get_ports {exp_p_io[2]}]
set_property PULLDOWN TRUE [get_ports {exp_p_io[3]}]
#### SATA connector #### SATA connector
#set_property IOSTANDARD LVCMOS18 [get_ports {daisy_p_o[*]}] #set_property IOSTANDARD LVCMOS18 [get_ports {daisy_p_o[*]}]
@ -227,7 +227,7 @@ set_multicycle_path 2 -from [get_ports {adc_dat_i[*][*]}]
# Digital inputs are asynchronous and captured in IOB flipflops. # Digital inputs are asynchronous and captured in IOB flipflops.
# Declare false path to avoid warning for unconstrained path. # Declare false path to avoid warning for unconstrained path.
set_false_path -from [get_ports {exp_p_io[*] exp_n_io[*]}] set_false_path -from [get_ports {exp_p_io[*]}]
# Delay to LEDs does not matter; just set a long max delay. # Delay to LEDs does not matter; just set a long max delay.
set_max_delay -to [get_ports {led_o[*]}] 20.0 set_max_delay -to [get_ports {led_o[*]}] 20.0

6
fpga/constraints/red_pitaya_4ch.xdc
View File

@ -148,9 +148,9 @@ set_property PACKAGE_PIN Y6 [get_ports {exp_n_io[10]}]
# Pull down digital inputs. # Pull down digital inputs.
set_property PULLDOWN TRUE [get_ports {exp_p_io[0]}] set_property PULLDOWN TRUE [get_ports {exp_p_io[0]}]
set_property PULLDOWN TRUE [get_ports {exp_n_io[0]}]
set_property PULLDOWN TRUE [get_ports {exp_p_io[1]}] set_property PULLDOWN TRUE [get_ports {exp_p_io[1]}]
set_property PULLDOWN TRUE [get_ports {exp_n_io[1]}] set_property PULLDOWN TRUE [get_ports {exp_p_io[2]}]
set_property PULLDOWN TRUE [get_ports {exp_p_io[3]}]
### PLL ### PLL
#set_property IOSTANDARD LVCMOS33 [get_ports pll_*] #set_property IOSTANDARD LVCMOS33 [get_ports pll_*]
@ -217,7 +217,7 @@ set_max_delay -from [get_clocks adc_clk_23] -to [get_clocks adc_clk_01] 6.4
# Digital inputs are asynchronous and captured in IOB flipflops. # Digital inputs are asynchronous and captured in IOB flipflops.
# Declare false path to avoid warning for unconstrained path. # Declare false path to avoid warning for unconstrained path.
set_false_path -from [get_ports {exp_p_io[*] exp_n_io[*]}] set_false_path -from [get_ports {exp_p_io[*]}]
# Delay to LEDs does not matter; just set a long max delay. # Delay to LEDs does not matter; just set a long max delay.
set_max_delay -to [get_ports {led_o[*]}] 20.0 set_max_delay -to [get_ports {led_o[*]}] 20.0

2
fpga/rtl/puzzlefw_pkg.vhd
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@ -96,7 +96,7 @@ package puzzlefw_pkg is
-- Firmware info word. -- Firmware info word.
constant fw_api_version: natural := 1; constant fw_api_version: natural := 1;
constant fw_version_major: natural := 0; constant fw_version_major: natural := 0;
constant fw_version_minor: natural := 15; constant fw_version_minor: natural := 16;
constant fw_info_word: std_logic_vector(31 downto 0) := constant fw_info_word: std_logic_vector(31 downto 0) :=
x"4a" x"4a"
& std_logic_vector(to_unsigned(fw_api_version, 8)) & std_logic_vector(to_unsigned(fw_api_version, 8))

6
fpga/rtl/puzzlefw_top.vhd
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@ -21,7 +21,6 @@ use work.puzzlefw_pkg.all;
entity puzzlefw_top is entity puzzlefw_top is
port ( port (
-- Ports directly connected to ARM/PS. -- Ports directly connected to ARM/PS.
DDR_0_addr: inout std_logic_vector(14 downto 0); DDR_0_addr: inout std_logic_vector(14 downto 0);
DDR_0_ba: inout std_logic_vector(2 downto 0); DDR_0_ba: inout std_logic_vector(2 downto 0);
@ -583,10 +582,7 @@ begin
out_data => s_acq_dma_data ); out_data => s_acq_dma_data );
-- Capture digital inputs. -- Capture digital inputs.
s_dig_in(0) <= exp_p_io(0); s_dig_in <= exp_p_io(3 downto 0);
s_dig_in(1) <= exp_n_io(0);
s_dig_in(2) <= exp_p_io(1);
s_dig_in(3) <= exp_n_io(1);
inst_dig_capture_gen: for i in 0 to 3 generate inst_dig_capture_gen: for i in 0 to 3 generate

5
fpga/rtl/puzzlefw_top_4ch.vhd
View File

@ -621,10 +621,7 @@ begin
out_data => s_acq_dma_data ); out_data => s_acq_dma_data );
-- Capture digital inputs. -- Capture digital inputs.
s_dig_in(0) <= exp_p_io(0); s_dig_in <= exp_p_io(3 downto 0);
s_dig_in(1) <= exp_n_io(0);
s_dig_in(2) <= exp_p_io(1);
s_dig_in(3) <= exp_n_io(1);
inst_dig_capture_gen: for i in 0 to 3 generate inst_dig_capture_gen: for i in 0 to 3 generate