diff --git a/fpga/constraints/red_pitaya.xdc b/fpga/constraints/red_pitaya.xdc
index 63f5ee7..9647cf1 100644
--- a/fpga/constraints/red_pitaya.xdc
+++ b/fpga/constraints/red_pitaya.xdc
@@ -171,9 +171,9 @@ set_property PACKAGE_PIN M15 [get_ports {exp_n_io[7]}]
 
 # Pull down digital inputs.
 set_property PULLDOWN TRUE [get_ports {exp_p_io[0]}]
-set_property PULLDOWN TRUE [get_ports {exp_n_io[0]}]
 set_property PULLDOWN TRUE [get_ports {exp_p_io[1]}]
-set_property PULLDOWN TRUE [get_ports {exp_n_io[1]}]
+set_property PULLDOWN TRUE [get_ports {exp_p_io[2]}]
+set_property PULLDOWN TRUE [get_ports {exp_p_io[3]}]
 
 #### SATA connector
 #set_property IOSTANDARD LVCMOS18 [get_ports {daisy_p_o[*]}]
@@ -227,7 +227,7 @@ set_multicycle_path 2 -from [get_ports {adc_dat_i[*][*]}]
 
 # Digital inputs are asynchronous and captured in IOB flipflops.
 # Declare false path to avoid warning for unconstrained path.
-set_false_path -from [get_ports {exp_p_io[*] exp_n_io[*]}]
+set_false_path -from [get_ports {exp_p_io[*]}]
 
 # Delay to LEDs does not matter; just set a long max delay.
 set_max_delay -to [get_ports {led_o[*]}] 20.0
diff --git a/fpga/constraints/red_pitaya_4ch.xdc b/fpga/constraints/red_pitaya_4ch.xdc
index 2f19d09..593c970 100644
--- a/fpga/constraints/red_pitaya_4ch.xdc
+++ b/fpga/constraints/red_pitaya_4ch.xdc
@@ -148,9 +148,9 @@ set_property PACKAGE_PIN Y6  [get_ports {exp_n_io[10]}]
 
 # Pull down digital inputs.
 set_property PULLDOWN TRUE [get_ports {exp_p_io[0]}]
-set_property PULLDOWN TRUE [get_ports {exp_n_io[0]}]
 set_property PULLDOWN TRUE [get_ports {exp_p_io[1]}]
-set_property PULLDOWN TRUE [get_ports {exp_n_io[1]}]
+set_property PULLDOWN TRUE [get_ports {exp_p_io[2]}]
+set_property PULLDOWN TRUE [get_ports {exp_p_io[3]}]
 
 ### PLL
 #set_property IOSTANDARD LVCMOS33 [get_ports pll_*]
@@ -217,7 +217,7 @@ set_max_delay -from [get_clocks adc_clk_23] -to [get_clocks adc_clk_01] 6.4
 
 # Digital inputs are asynchronous and captured in IOB flipflops.
 # Declare false path to avoid warning for unconstrained path.
-set_false_path -from [get_ports {exp_p_io[*] exp_n_io[*]}]
+set_false_path -from [get_ports {exp_p_io[*]}]
 
 # Delay to LEDs does not matter; just set a long max delay.
 set_max_delay -to [get_ports {led_o[*]}] 20.0
diff --git a/fpga/rtl/puzzlefw_pkg.vhd b/fpga/rtl/puzzlefw_pkg.vhd
index acdc623..92b13b8 100644
--- a/fpga/rtl/puzzlefw_pkg.vhd
+++ b/fpga/rtl/puzzlefw_pkg.vhd
@@ -96,7 +96,7 @@ package puzzlefw_pkg is
     -- Firmware info word.
     constant fw_api_version:        natural := 1;
     constant fw_version_major:      natural := 0;
-    constant fw_version_minor:      natural := 15;
+    constant fw_version_minor:      natural := 16;
     constant fw_info_word:          std_logic_vector(31 downto 0) :=
         x"4a"
         & std_logic_vector(to_unsigned(fw_api_version, 8))
diff --git a/fpga/rtl/puzzlefw_top.vhd b/fpga/rtl/puzzlefw_top.vhd
index 79e99bb..f9f8253 100644
--- a/fpga/rtl/puzzlefw_top.vhd
+++ b/fpga/rtl/puzzlefw_top.vhd
@@ -21,7 +21,6 @@ use work.puzzlefw_pkg.all;
 entity puzzlefw_top is
 
     port (
-
         -- Ports directly connected to ARM/PS.
         DDR_0_addr:         inout std_logic_vector(14 downto 0);
         DDR_0_ba:           inout std_logic_vector(2 downto 0);
@@ -583,10 +582,7 @@ begin
             out_data            => s_acq_dma_data );
 
     -- Capture digital inputs.
-    s_dig_in(0) <= exp_p_io(0);
-    s_dig_in(1) <= exp_n_io(0);
-    s_dig_in(2) <= exp_p_io(1);
-    s_dig_in(3) <= exp_n_io(1);
+    s_dig_in <= exp_p_io(3 downto 0);
 
     inst_dig_capture_gen: for i in 0 to 3 generate
 
diff --git a/fpga/rtl/puzzlefw_top_4ch.vhd b/fpga/rtl/puzzlefw_top_4ch.vhd
index f8dd2a7..b47051e 100644
--- a/fpga/rtl/puzzlefw_top_4ch.vhd
+++ b/fpga/rtl/puzzlefw_top_4ch.vhd
@@ -621,10 +621,7 @@ begin
             out_data            => s_acq_dma_data );
 
     -- Capture digital inputs.
-    s_dig_in(0) <= exp_p_io(0);
-    s_dig_in(1) <= exp_n_io(0);
-    s_dig_in(2) <= exp_p_io(1);
-    s_dig_in(3) <= exp_n_io(1);
+    s_dig_in <= exp_p_io(3 downto 0);
 
     inst_dig_capture_gen: for i in 0 to 3 generate