joris
/
redpitaya-puzzlefw
1
0
Fork 0
Code Issues Pull Requests Releases Activity

fix

This commit is contained in:
Joris van Rantwijk 2024-10-12 10:55:41 +02:00
parent d9ff515723
commit 186d41df10
1 changed files with 9 additions and 7 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

16
doc/fpga_firmware.md
View File

@ -219,13 +219,7 @@ It marks the point in the message sequence where an unknown number of messages h
The timetagger has 4 digital input signals. The timetagger has 4 digital input signals.
If a rising or falling edge occurs on one of these signals, a timestamp is assigned to that event. If a rising or falling edge occurs on one of these signals, a timestamp is assigned to that event.
Timestamped events are transferred via DMA. Timestamped event messages are transferred via DMA.
The 4 digital input channels are connected to the digital I/O connector of the Red Pitaya.
Digital input channels 0 to 3 correspond to pins `DIO0_P` to `DIO3_P`.
A 4-cycle glitch filter is applied to the digital input signals.
This filter rejects digital pulses shorter than 4 clock cycles (32 ns).
Messages are only emitted for _enabled_ event types. Messages are only emitted for _enabled_ event types.
Rising edges and falling edges can be separately enabled or disabled for each digital input channel. Rising edges and falling edges can be separately enabled or disabled for each digital input channel.
@ -235,6 +229,14 @@ The messages are queued in a FIFO buffer inside the FPGA before being transferre
This FIFO is necessary to hold messages for a short time while the DMA engine sets up a DMA transfer. This FIFO is necessary to hold messages for a short time while the DMA engine sets up a DMA transfer.
It has room for 4096 messages. It has room for 4096 messages.
## Digital input signals
The 4 digital input channels are connected to the digital I/O connector of the Red Pitaya.
Digital input channels 0 to 3 correspond to pins `DIO0_P` to `DIO3_P`.
A 4-cycle glitch filter is applied to the digital input signals.
This filter rejects digital pulses shorter than 4 clock cycles (32 ns).
## Output data format ## Output data format
The output from the timetagger is a sequence of 64-bit messages. The output from the timetagger is a sequence of 64-bit messages.