From 186d41df10c0667bc2ab9a87196018b9f62db0d6 Mon Sep 17 00:00:00 2001 From: Joris van Rantwijk Date: Sat, 12 Oct 2024 10:55:41 +0200 Subject: [PATCH] fix --- doc/fpga_firmware.md | 16 +++++++++------- 1 file changed, 9 insertions(+), 7 deletions(-) diff --git a/doc/fpga_firmware.md b/doc/fpga_firmware.md index 8abf13f..ee7204e 100644 --- a/doc/fpga_firmware.md +++ b/doc/fpga_firmware.md @@ -219,13 +219,7 @@ It marks the point in the message sequence where an unknown number of messages h The timetagger has 4 digital input signals. If a rising or falling edge occurs on one of these signals, a timestamp is assigned to that event. -Timestamped events are transferred via DMA. - -The 4 digital input channels are connected to the digital I/O connector of the Red Pitaya. -Digital input channels 0 to 3 correspond to pins `DIO0_P` to `DIO3_P`. - -A 4-cycle glitch filter is applied to the digital input signals. -This filter rejects digital pulses shorter than 4 clock cycles (32 ns). +Timestamped event messages are transferred via DMA. Messages are only emitted for _enabled_ event types. Rising edges and falling edges can be separately enabled or disabled for each digital input channel. @@ -235,6 +229,14 @@ The messages are queued in a FIFO buffer inside the FPGA before being transferre This FIFO is necessary to hold messages for a short time while the DMA engine sets up a DMA transfer. It has room for 4096 messages. +## Digital input signals + +The 4 digital input channels are connected to the digital I/O connector of the Red Pitaya. +Digital input channels 0 to 3 correspond to pins `DIO0_P` to `DIO3_P`. + +A 4-cycle glitch filter is applied to the digital input signals. +This filter rejects digital pulses shorter than 4 clock cycles (32 ns). + ## Output data format The output from the timetagger is a sequence of 64-bit messages.