40 lines
713 B
VHDL
40 lines
713 B
VHDL
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--
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-- Double flip-flop synchronizer.
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--
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library ieee;
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use ieee.std_logic_1164.all;
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library xpm;
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use xpm.vcomponents.all;
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entity syncdff is
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port (
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-- Clock (destination domain).
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clk: in std_logic;
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-- Input data (asynchronous).
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di: in std_logic;
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-- Output data, synchronous to "clk".
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do: out std_logic
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);
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end entity;
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architecture rtl of syncdff is
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begin
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inst: xpm_cdc_single
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generic map (
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DEST_SYNC_FF => 2,
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SRC_INPUT_REG => 0 )
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port map (
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dest_clk => clk,
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dest_out => do,
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src_clk => '0',
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src_in => di );
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end architecture;
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