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redpitaya-puzzlefw/fpga/vivado/redpitaya_puzzlefw.xpr

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Add Vivado project
2024-08-02 22:14:19 +02:00
<?xml version="1.0" encoding="UTF-8"?>
<!-- Product Version: Vivado v2020.2 (64-bit) -->
<!-- -->
<!-- Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. -->
<Project Version="7" Minor="54" Path="/home/joris/proj/redpitaya-puzzlefw/fpga/vivado/redpitaya_puzzlefw.xpr">
<DefaultLaunch Dir="$PRUNDIR"/>
<Configuration>
<Option Name="Id" Val="6bfdf9fdb55b4f6590ea35b5ab916bb3"/>
<Option Name="Part" Val="xc7z010clg400-1"/>
<Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
<Option Name="CompiledLibDirXSim" Val=""/>
<Option Name="CompiledLibDirModelSim" Val="$PCACHEDIR/compile_simlib/modelsim"/>
<Option Name="CompiledLibDirQuesta" Val="$PCACHEDIR/compile_simlib/questa"/>
<Option Name="CompiledLibDirIES" Val="$PCACHEDIR/compile_simlib/ies"/>
<Option Name="CompiledLibDirXcelium" Val="$PCACHEDIR/compile_simlib/xcelium"/>
<Option Name="CompiledLibDirVCS" Val="$PCACHEDIR/compile_simlib/vcs"/>
<Option Name="CompiledLibDirRiviera" Val="$PCACHEDIR/compile_simlib/riviera"/>
<Option Name="CompiledLibDirActivehdl" Val="$PCACHEDIR/compile_simlib/activehdl"/>
<Option Name="SimulatorInstallDirModelSim" Val=""/>
<Option Name="SimulatorInstallDirQuesta" Val=""/>
<Option Name="SimulatorInstallDirIES" Val=""/>
<Option Name="SimulatorInstallDirXcelium" Val=""/>
<Option Name="SimulatorInstallDirVCS" Val=""/>
<Option Name="SimulatorInstallDirRiviera" Val=""/>
<Option Name="SimulatorInstallDirActiveHdl" Val=""/>
<Option Name="SimulatorGccInstallDirModelSim" Val=""/>
<Option Name="SimulatorGccInstallDirQuesta" Val=""/>
<Option Name="SimulatorGccInstallDirIES" Val=""/>
<Option Name="SimulatorGccInstallDirXcelium" Val=""/>
<Option Name="SimulatorGccInstallDirVCS" Val=""/>
<Option Name="SimulatorGccInstallDirRiviera" Val=""/>
<Option Name="SimulatorGccInstallDirActiveHdl" Val=""/>
<Option Name="TargetLanguage" Val="VHDL"/>
Update block design and Vivado project Remove block RAM from block design. Update Vivado project file.
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<Option Name="BoardPart" Val="redpitaya.com:redpitaya:part0:1.1"/>
Add Vivado project
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<Option Name="ActiveSimSet" Val="sim_1"/>
<Option Name="DefaultLib" Val="xil_defaultlib"/>
<Option Name="ProjectType" Val="Default"/>
<Option Name="IPOutputRepo" Val="$PCACHEDIR/ip"/>
<Option Name="IPDefaultOutputPath" Val="$PGENDIR/sources_1"/>
<Option Name="IPCachePermission" Val="read"/>
<Option Name="IPCachePermission" Val="write"/>
<Option Name="EnableCoreContainer" Val="FALSE"/>
<Option Name="CreateRefXciForCoreContainers" Val="FALSE"/>
<Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
<Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
<Option Name="EnableBDX" Val="FALSE"/>
Update block design and Vivado project Remove block RAM from block design. Update Vivado project file.
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<Option Name="DSABoardId" Val="redpitaya"/>
Add Vivado project
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<Option Name="WTXSimLaunchSim" Val="0"/>
<Option Name="WTModelSimLaunchSim" Val="0"/>
<Option Name="WTQuestaLaunchSim" Val="0"/>
<Option Name="WTIesLaunchSim" Val="0"/>
<Option Name="WTVcsLaunchSim" Val="0"/>
<Option Name="WTRivieraLaunchSim" Val="0"/>
<Option Name="WTActivehdlLaunchSim" Val="0"/>
<Option Name="WTXSimExportSim" Val="1"/>
<Option Name="WTModelSimExportSim" Val="1"/>
<Option Name="WTQuestaExportSim" Val="1"/>
<Option Name="WTIesExportSim" Val="1"/>
<Option Name="WTVcsExportSim" Val="1"/>
<Option Name="WTRivieraExportSim" Val="1"/>
<Option Name="WTActivehdlExportSim" Val="1"/>
<Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
<Option Name="XSimRadix" Val="hex"/>
<Option Name="XSimTimeUnit" Val="ns"/>
<Option Name="XSimArrayDisplayLimit" Val="1024"/>
<Option Name="XSimTraceLimit" Val="65536"/>
<Option Name="SimTypes" Val="rtl"/>
<Option Name="SimTypes" Val="bfm"/>
<Option Name="SimTypes" Val="tlm"/>
<Option Name="SimTypes" Val="tlm_dpi"/>
<Option Name="MEMEnableMemoryMapGeneration" Val="TRUE"/>
<Option Name="DcpsUptoDate" Val="TRUE"/>
</Configuration>
<FileSets Version="1" Minor="31">
<FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1" RelGenDir="$PGENDIR/sources_1">
<Filter Type="Srcs"/>
<File Path="$PSRCDIR/sources_1/bd/puzzlefw/puzzlefw.bd">
<FileInfo>
<Attr Name="ImportPath" Val="$PPRDIR/../puzzlefw/puzzlefw.bd"/>
<Attr Name="ImportTime" Val="1722629191"/>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
Add timetagger logic to Vivado project
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<CompFileExtendedInfo CompFileName="puzzlefw.bd" FileRelPathName="ip/puzzlefw_processing_system7_0_0/puzzlefw_processing_system7_0_0.xci">
<Proxy FileSetName="puzzlefw_processing_system7_0_0"/>
Add Vivado project
2024-08-02 22:14:19 +02:00
</CompFileExtendedInfo>
Update block design and Vivado project Remove block RAM from block design. Update Vivado project file.
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<CompFileExtendedInfo CompFileName="puzzlefw.bd" FileRelPathName="ip/puzzlefw_proc_sys_reset_0_0/puzzlefw_proc_sys_reset_0_0.xci">
<Proxy FileSetName="puzzlefw_proc_sys_reset_0_0"/>
Add Vivado project
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</CompFileExtendedInfo>
Add timetagger logic to Vivado project
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<CompFileExtendedInfo CompFileName="puzzlefw.bd" FileRelPathName="ip/puzzlefw_axi_apb_bridge_0_0/puzzlefw_axi_apb_bridge_0_0.xci">
<Proxy FileSetName="puzzlefw_axi_apb_bridge_0_0"/>
Add Vivado project
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</CompFileExtendedInfo>
</File>
<File Path="$PGENDIR/sources_1/bd/puzzlefw/hdl/puzzlefw_wrapper.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../rtl/puzzlefw_pkg.vhd">
<FileInfo SFType="VHDL2008">
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
Update block design and Vivado project Remove block RAM from block design. Update Vivado project file.
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<File Path="$PPRDIR/../rtl/trigger_detector.vhd">
<FileInfo SFType="VHDL2008">
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../rtl/acquisition_manager.vhd">
<FileInfo SFType="VHDL2008">
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../rtl/shift_engine.vhd">
<FileInfo SFType="VHDL2008">
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../rtl/sample_decimation.vhd">
<FileInfo SFType="VHDL2008">
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../rtl/acquisition_stream.vhd">
<FileInfo SFType="VHDL2008">
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../rtl/acquisition_chain.vhd">
<FileInfo SFType="VHDL2008">
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../rtl/adc_capture.vhd">
<FileInfo SFType="VHDL2008">
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../rtl/adc_range_monitor.vhd">
<FileInfo SFType="VHDL2008">
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../rtl/adc_sample_stream.vhd">
<FileInfo SFType="VHDL2008">
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
Add timetagger logic to Vivado project
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<File Path="$PPRDIR/../rtl/deglitch.vhd">
<FileInfo SFType="VHDL2008">
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
Add Vivado project
2024-08-02 22:14:19 +02:00
<File Path="$PPRDIR/../rtl/dma_axi_master.vhd">
<FileInfo SFType="VHDL2008">
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
Update block design and Vivado project Remove block RAM from block design. Update Vivado project file.
2024-08-27 18:55:25 +02:00
<File Path="$PPRDIR/../rtl/simple_fifo.vhd">
<FileInfo SFType="VHDL2008">
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../rtl/dma_write_channel.vhd">
<FileInfo SFType="VHDL2008">
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
Add Vivado project
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<File Path="$PPRDIR/../rtl/registers.vhd">
<FileInfo SFType="VHDL2008">
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
Update block design and Vivado project Remove block RAM from block design. Update Vivado project file.
2024-08-27 18:55:25 +02:00
<File Path="$PPRDIR/../rtl/timestamp_gen.vhd">
<FileInfo SFType="VHDL2008">
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
Add timetagger logic to Vivado project
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<File Path="$PPRDIR/../rtl/syncdff.vhd">
<FileInfo SFType="VHDL2008">
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../rtl/timetagger.vhd">
<FileInfo SFType="VHDL2008">
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
Add Vivado project
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<File Path="$PPRDIR/../rtl/puzzlefw_top.vhd">
<FileInfo SFType="VHDL2008">
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<Config>
<Option Name="DesignMode" Val="RTL"/>
<Option Name="TopModule" Val="puzzlefw_top"/>
<Option Name="TopAutoSet" Val="TRUE"/>
</Config>
</FileSet>
<FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1" RelGenDir="$PGENDIR/constrs_1">
<Filter Type="Constrs"/>
<File Path="$PPRDIR/../constraints/red_pitaya.xdc">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
</FileInfo>
</File>
<Config>
<Option Name="ConstrsType" Val="XDC"/>
</Config>
</FileSet>
<FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1" RelGenDir="$PGENDIR/sim_1">
<Filter Type="Srcs"/>
<Config>
<Option Name="DesignMode" Val="RTL"/>
<Option Name="TopModule" Val="puzzlefw_top"/>
<Option Name="TopLib" Val="xil_defaultlib"/>
<Option Name="TopAutoSet" Val="TRUE"/>
<Option Name="TransportPathDelay" Val="0"/>
<Option Name="TransportIntDelay" Val="0"/>
<Option Name="SelectedSimModel" Val="rtl"/>
<Option Name="PamDesignTestbench" Val=""/>
<Option Name="PamDutBypassFile" Val="xil_dut_bypass"/>
<Option Name="PamSignalDriverFile" Val="xil_bypass_driver"/>
<Option Name="PamPseudoTop" Val="pseudo_tb"/>
<Option Name="SrcSet" Val="sources_1"/>
</Config>
</FileSet>
<FileSet Name="utils_1" Type="Utils" RelSrcDir="$PSRCDIR/utils_1" RelGenDir="$PGENDIR/utils_1">
<Filter Type="Utils"/>
<Config>
<Option Name="TopAutoSet" Val="TRUE"/>
</Config>
</FileSet>
<FileSet Name="puzzlefw_processing_system7_0_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/puzzlefw_processing_system7_0_0" RelGenDir="$PGENDIR/puzzlefw_processing_system7_0_0">
<Config>
<Option Name="TopModule" Val="puzzlefw_processing_system7_0_0"/>
<Option Name="UseBlackboxStub" Val="1"/>
</Config>
</FileSet>
<FileSet Name="puzzlefw_proc_sys_reset_0_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/puzzlefw_proc_sys_reset_0_0" RelGenDir="$PGENDIR/puzzlefw_proc_sys_reset_0_0">
<Config>
<Option Name="TopModule" Val="puzzlefw_proc_sys_reset_0_0"/>
<Option Name="UseBlackboxStub" Val="1"/>
</Config>
</FileSet>
<FileSet Name="puzzlefw_axi_apb_bridge_0_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/puzzlefw_axi_apb_bridge_0_0" RelGenDir="$PGENDIR/puzzlefw_axi_apb_bridge_0_0">
<Config>
<Option Name="TopModule" Val="puzzlefw_axi_apb_bridge_0_0"/>
<Option Name="UseBlackboxStub" Val="1"/>
</Config>
</FileSet>
</FileSets>
<Simulators>
<Simulator Name="XSim">
<Option Name="Description" Val="Vivado Simulator"/>
<Option Name="CompiledLib" Val="0"/>
</Simulator>
<Simulator Name="ModelSim">
<Option Name="Description" Val="ModelSim Simulator"/>
</Simulator>
<Simulator Name="Questa">
<Option Name="Description" Val="Questa Advanced Simulator"/>
</Simulator>
<Simulator Name="IES">
<Option Name="Description" Val="Incisive Enterprise Simulator (IES)"/>
</Simulator>
<Simulator Name="Xcelium">
<Option Name="Description" Val="Xcelium Parallel Simulator"/>
</Simulator>
<Simulator Name="VCS">
<Option Name="Description" Val="Verilog Compiler Simulator (VCS)"/>
</Simulator>
<Simulator Name="Riviera">
<Option Name="Description" Val="Riviera-PRO Simulator"/>
</Simulator>
</Simulators>
<Runs Version="1" Minor="15">
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7z010clg400-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/synth_1" IncludeInArchive="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2020"/>
<Step Id="synth_design"/>
</Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2020"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="puzzlefw_processing_system7_0_0_synth_1" Type="Ft3:Synth" SrcSet="puzzlefw_processing_system7_0_0" Part="xc7z010clg400-1" ConstrsSet="puzzlefw_processing_system7_0_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/puzzlefw_processing_system7_0_0_synth_1" IncludeInArchive="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/puzzlefw_processing_system7_0_0_synth_1">
<Strategy Version="1" Minor="2">
Update block design and Vivado project Remove block RAM from block design. Update Vivado project file.
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<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2020"/>
Add Vivado project
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<Step Id="synth_design"/>
</Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2020"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="puzzlefw_proc_sys_reset_0_0_synth_1" Type="Ft3:Synth" SrcSet="puzzlefw_proc_sys_reset_0_0" Part="xc7z010clg400-1" ConstrsSet="puzzlefw_proc_sys_reset_0_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/puzzlefw_proc_sys_reset_0_0_synth_1" IncludeInArchive="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/puzzlefw_proc_sys_reset_0_0_synth_1">
<Strategy Version="1" Minor="2">
Update block design and Vivado project Remove block RAM from block design. Update Vivado project file.
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<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2020"/>
Add Vivado project
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<Step Id="synth_design"/>
</Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2020"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="puzzlefw_axi_apb_bridge_0_0_synth_1" Type="Ft3:Synth" SrcSet="puzzlefw_axi_apb_bridge_0_0" Part="xc7z010clg400-1" ConstrsSet="puzzlefw_axi_apb_bridge_0_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/puzzlefw_axi_apb_bridge_0_0_synth_1" IncludeInArchive="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/puzzlefw_axi_apb_bridge_0_0_synth_1">
<Strategy Version="1" Minor="2">
Update block design and Vivado project Remove block RAM from block design. Update Vivado project file.
2024-08-27 18:55:25 +02:00
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2020"/>
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<Step Id="synth_design"/>
</Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2020"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
Add timetagger logic to Vivado project
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<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7z010clg400-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/impl_1" SynthRun="synth_1" IncludeInArchive="true" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1">
Add Vivado project
2024-08-02 22:14:19 +02:00
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2020"/>
<Step Id="init_design"/>
<Step Id="opt_design"/>
<Step Id="power_opt_design"/>
<Step Id="place_design"/>
<Step Id="post_place_power_opt_design"/>
<Step Id="phys_opt_design"/>
<Step Id="route_design"/>
<Step Id="post_route_phys_opt_design"/>
<Step Id="write_bitstream"/>
</Strategy>
Add timetagger logic to Vivado project
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<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
Add Vivado project
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<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2020"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="puzzlefw_processing_system7_0_0_impl_1" Type="Ft2:EntireDesign" Part="xc7z010clg400-1" ConstrsSet="puzzlefw_processing_system7_0_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="puzzlefw_processing_system7_0_0_synth_1" IncludeInArchive="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/puzzlefw_processing_system7_0_0_impl_1">
<Strategy Version="1" Minor="2">
Update block design and Vivado project Remove block RAM from block design. Update Vivado project file.
2024-08-27 18:55:25 +02:00
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2020"/>
Add Vivado project
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<Step Id="init_design"/>
<Step Id="opt_design"/>
<Step Id="power_opt_design"/>
<Step Id="place_design"/>
<Step Id="post_place_power_opt_design"/>
<Step Id="phys_opt_design"/>
<Step Id="route_design"/>
<Step Id="post_route_phys_opt_design"/>
<Step Id="write_bitstream"/>
</Strategy>
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2020"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="puzzlefw_proc_sys_reset_0_0_impl_1" Type="Ft2:EntireDesign" Part="xc7z010clg400-1" ConstrsSet="puzzlefw_proc_sys_reset_0_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="puzzlefw_proc_sys_reset_0_0_synth_1" IncludeInArchive="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/puzzlefw_proc_sys_reset_0_0_impl_1">
<Strategy Version="1" Minor="2">
Update block design and Vivado project Remove block RAM from block design. Update Vivado project file.
2024-08-27 18:55:25 +02:00
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2020"/>
Add Vivado project
2024-08-02 22:14:19 +02:00
<Step Id="init_design"/>
<Step Id="opt_design"/>
<Step Id="power_opt_design"/>
<Step Id="place_design"/>
<Step Id="post_place_power_opt_design"/>
<Step Id="phys_opt_design"/>
<Step Id="route_design"/>
<Step Id="post_route_phys_opt_design"/>
<Step Id="write_bitstream"/>
</Strategy>
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2020"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="puzzlefw_axi_apb_bridge_0_0_impl_1" Type="Ft2:EntireDesign" Part="xc7z010clg400-1" ConstrsSet="puzzlefw_axi_apb_bridge_0_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="puzzlefw_axi_apb_bridge_0_0_synth_1" IncludeInArchive="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/puzzlefw_axi_apb_bridge_0_0_impl_1">
<Strategy Version="1" Minor="2">
Update block design and Vivado project Remove block RAM from block design. Update Vivado project file.
2024-08-27 18:55:25 +02:00
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2020"/>
Add Vivado project
2024-08-02 22:14:19 +02:00
<Step Id="init_design"/>
<Step Id="opt_design"/>
<Step Id="power_opt_design"/>
<Step Id="place_design"/>
<Step Id="post_place_power_opt_design"/>
<Step Id="phys_opt_design"/>
<Step Id="route_design"/>
<Step Id="post_route_phys_opt_design"/>
<Step Id="write_bitstream"/>
</Strategy>
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2020"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
</Runs>
Update block design and Vivado project Remove block RAM from block design. Update Vivado project file.
2024-08-27 18:55:25 +02:00
<Board>
<Jumpers>
<Jumper Name="IN1" Val="false"/>
<Jumper Name="IN2" Val="false"/>
</Jumpers>
</Board>
Add Vivado project
2024-08-02 22:14:19 +02:00
<DashboardSummary Version="1" Minor="0">
<Dashboards>
<Dashboard Name="default_dashboard">
<Gadgets>
<Gadget Name="drc_1" Type="drc" Version="1" Row="2" Column="0">
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_drc_0 "/>
</Gadget>
<Gadget Name="methodology_1" Type="methodology" Version="1" Row="2" Column="1">
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_methodology_0 "/>
</Gadget>
<Gadget Name="power_1" Type="power" Version="1" Row="1" Column="0">
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_power_0 "/>
</Gadget>
<Gadget Name="timing_1" Type="timing" Version="1" Row="0" Column="1">
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_timing_summary_0 "/>
</Gadget>
<Gadget Name="utilization_1" Type="utilization" Version="1" Row="0" Column="0">
<GadgetParam Name="REPORTS" Type="string_list" Value="synth_1#synth_1_synth_report_utilization_0 "/>
<GadgetParam Name="RUN.STEP" Type="string" Value="synth_design"/>
<GadgetParam Name="RUN.TYPE" Type="string" Value="synthesis"/>
</Gadget>
<Gadget Name="utilization_2" Type="utilization" Version="1" Row="1" Column="1">
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_place_report_utilization_0 "/>
</Gadget>
</Gadgets>
</Dashboard>
<CurrentDashboard>default_dashboard</CurrentDashboard>
</Dashboards>
</DashboardSummary>
</Project>