Signed multiplier in VHDL or Verilog

Joris van Rantwijk 73c857b92d Add VHDL testbench and makefile for simulation with GHDL.		2016-03-07 21:59:26 +01:00
vhdl_sim	Add VHDL testbench and makefile for simulation with GHDL.	2016-03-07 21:59:26 +01:00
genmul.py	Python script to generate multiplier code.	2016-03-07 21:55:26 +01:00
smul8.vhdl	Add example of VHDL output file.	2016-03-07 21:57:38 +01:00