1031 lines
25 KiB
Python
1031 lines
25 KiB
Python
"""
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Generate VHDL or Verilog code for a signed multiplier.
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Usage: genmul.py --lang=vhdl|verilog [--nolib] Xbits Ybits npipe
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Usage: genmul.py --lang=vhdl|verilog --lib
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--lang=... Specify VHDL or Verilog code
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--nolib Do not generate library components
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--lib Generate only library components
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Xbits Length of input word in bits (Xbits >= 4)
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Ybits Length of input word in bits (Ybits >= Xbits)
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npipe Number of register stages (0 or 1 or 2)
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See also:
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G. Knagge, "ASIC Design for Signal Processing",
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http://www.geoffknagge.com/fyp/booth.shtml, 2010.
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X. Xiong, M. Lin, "Low Power 8-bit Baugh-Wooley Multiplier Based on Wallace
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Tree Architecture", Lecture Notes in Electrical Engineering, 2012.
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L. Dadda, "Some schemes for parallel multipliers",
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Associazione Elettrotecnica et Elettronica Italiana, 1965.
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R. P. Brent, H. T. Kung, "A Regular Layout for Parallel Adders",
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IEEE Transactions on Computers, 1982.
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"""
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import sys
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import argparse
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class Expr:
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"""Represent a node in the expression tree."""
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wire = None
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done = False
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class ConstBit(Expr):
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"""Represent constant '0' or '1' bit."""
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def __init__(self, v):
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assert v in (0, 1)
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self.v = v
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class InBit(Expr):
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"""Represent an input bit in the expression tree."""
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def __init__(self, xy, p):
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assert xy in ('x', 'y')
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self.xy = xy
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self.p = p
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class Reg(Expr):
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"""Represent flip-flop."""
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def __init__(self, v):
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self.v = v
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class NotBit(Expr):
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"""Represent inverter."""
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def __init__(self, v):
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self.v = v
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class BoothNeg(Expr):
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"""Represent calculation of radix-4 Booth sign-inversion flag."""
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def __init__(self, pat):
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assert len(pat) == 3
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self.pat = pat
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class BoothProd(Expr):
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"""Represent calculation of partial product bit with radix-4 Booth."""
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def __init__(self, pat, b):
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assert len(pat) == 3
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assert len(b) == 2
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self.pat = pat
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self.b = b
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class AddBitD(Expr):
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"""Represent selection of data bit from adder."""
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def __init__(self, v):
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self.v = v
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class AddBitC(Expr):
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"""Represent selection of carry bit from adder."""
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def __init__(self, v):
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self.v = v
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class HalfAdd(Expr):
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"""Represent half adder."""
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def __init__(self, a, b):
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self.a = a
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self.b = b
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class FullAdd(Expr):
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"""Represent full adder."""
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def __init__(self, a, b, c):
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self.a = a
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self.b = b
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self.c = c
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class CarryProp(Expr):
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"""Represent base node of carry propagation tree."""
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def __init__(self, a, b):
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self.a = a
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self.b = b
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class CarryMerge(Expr):
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"""Represent internal node of carry propagation tree."""
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def __init__(self, p0, p1):
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self.p0 = p0
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self.p1 = p1
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class CarryEval(Expr):
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"""Represent logic to calculate carry-out."""
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def __init__(self, p, c):
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self.p = p
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self.c = c
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def gen_partial_products(xvec, yvec):
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"""Generate list of partial products using radix-4 Booth algorithm.
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Return [ (exponent, bit), ... ].
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"""
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partial_products = [ ]
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# Append zero on LSB side of xvec, sign-extend on MSB side of xvec.
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xtmp = [ ConstBit(0) ] + xvec + xvec[-1:]
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# Append zero on LSB side of yvec, sign-extend on MSB side of yvec.
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ytmp = [ ConstBit(0) ] + yvec + yvec[-1:]
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# Step through xvec, 2 bits at a time.
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for i in xrange(0, len(xvec), 2):
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# Select group of 3 bits from xvec (one bit overlap with last group).
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pat = xtmp[i:i+3]
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# Add either 0, +1, +2, -1 or -2 times yvec according to Booth method.
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# Step through the bits of yvec.
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for j in xrange(len(yvec)+1):
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# Use Booth encoder to choose between 0, yvec[j], yvec[j-1] or
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# inverted bits yvec[j] or yvec[j-1].
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t = BoothProd(pat, ytmp[j:j+2])
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# Invert the MSB bit, except on first row.
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if i > 0 and j == len(yvec):
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t = NotBit(t)
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# Add result as partial product.
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partial_products.append( (i+j, t) )
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# For first row, sign-extend by two bits.
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# Apply sign inversion on the new MSB bit.
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if i == 0:
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partial_products.append( (i+len(yvec)+1, t) )
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partial_products.append( (i+len(yvec)+2, NotBit(t)) )
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# For each row except the first row, add constant 1 in the next column.
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if i > 0:
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partial_products.append( (i+len(yvec)+1, ConstBit(1)) )
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# Use Booth encoder to add 1 in case of negative factor (-1 or -2).
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t = BoothNeg(pat)
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partial_products.append( (i, t) )
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return partial_products
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def gen_dadda_tree(partial_products, nbits):
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"""Generate carry save adder based on Dadda tree."""
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# Sort partial products by bit position.
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tvec = [ [ ] for p in xrange(nbits) ]
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for (p, b) in partial_products:
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if p < nbits:
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tvec[p].append(b)
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# Build Dadda tree.
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while any([ len(t) > 3 for t in tvec ]):
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# New layer.
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nvec = [ [ ] for p in xrange(nbits+1) ]
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for p in xrange(nbits):
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t = tvec[p]
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i = 0
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while i + 2 < len(t):
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# build full adder
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a = FullAdd(t[i], t[i+1], t[i+2])
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nvec[p].append(AddBitD(a))
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nvec[p+1].append(AddBitC(a))
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i += 3
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if i + 1 < len(t) and len(nvec[p]) % 3 == 2:
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# build half adder
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a = HalfAdd(t[i], t[i+1])
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nvec[p].append(AddBitD(a))
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nvec[p+1].append(AddBitC(a))
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i += 2
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if i < len(t):
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# pass through
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nvec[p] += t[i:]
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tvec = nvec[:nbits]
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# Last layer.
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nvec = [ [ ] for p in xrange(nbits+1) ]
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for p in xrange(nbits):
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t = tvec[p]
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if len(t) == 3:
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# full adder
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a = FullAdd(t[0], t[1], t[2])
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nvec[p].append(AddBitD(a))
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nvec[p+1].append(AddBitC(a))
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elif len(t) == 2 and len(nvec[p]) > 0:
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# half adder
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a = HalfAdd(t[0], t[1])
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nvec[p].append(AddBitD(a))
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nvec[p+1].append(AddBitC(a))
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else:
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# pass through
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nvec[p] += t
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tvec = nvec[:nbits]
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# Extract remaining two rows of bits.
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avec = [ (t[0] if len(t) > 0 else ConstBit(0)) for t in tvec ]
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bvec = [ (t[1] if len(t) > 1 else ConstBit(0)) for t in tvec ]
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return (avec, bvec)
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def gen_adder(avec, bvec):
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"""Generate carry-lookahead adder."""
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def carry_lookahead(pvec, cin):
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"""Recursively determine carry propagation."""
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if len(pvec) == 1:
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prop = pvec[0]
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cvec = [ cin ]
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else:
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k = (len(pvec) + 1) // 2
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(p0, c0) = carry_lookahead(pvec[:k], cin)
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ctmp = CarryEval(p0, cin)
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(p1, c1) = carry_lookahead(pvec[k:], ctmp)
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prop = CarryMerge(p0, p1)
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cvec = c0 + c1
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return (prop, cvec)
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assert len(avec) == len(bvec)
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# Determine carry-generate and carry-propagate for each position.
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pvec = [ CarryProp(a, b) for (a, b) in zip(avec, bvec) ]
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# Determine carry-in for each position.
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(prop, cvec) = carry_lookahead(pvec, ConstBit(0))
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# Array of full adders.
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sumvec = [ AddBitD(FullAdd(a, b, c))
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for (a, b, c) in zip(avec, bvec, cvec) ]
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return sumvec
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def gen_multiplier(xbits, ybits, npipe):
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"""Generate expression tree describing multiplier logic."""
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xvec = [ InBit('x', p) for p in xrange(xbits) ]
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yvec = [ InBit('y', p) for p in xrange(ybits) ]
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partial_products = gen_partial_products(xvec, yvec)
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(avec, bvec) = gen_dadda_tree(partial_products, xbits+ybits)
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if npipe > 0:
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avec = [ Reg(a) for a in avec ]
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bvec = [ Reg(b) for b in bvec ]
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zvec = gen_adder(avec, bvec)
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if npipe > 1:
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zvec = [ Reg(z) for z in zvec ]
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return zvec
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def gen_netlist(node, wires, insts):
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"""Generate netlist consisting of wires and component instances."""
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if node.done:
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# already processed this node
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return
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node.done = True
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if isinstance(node, ConstBit):
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# resolve during code generation
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node.wire = node
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elif isinstance(node, InBit):
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# resolve during code generation
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node.wire = node
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elif isinstance(node, Reg):
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# create output wire
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node.wire = 'wreg%d' % len(wires)
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wires.append(node.wire)
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# recurse
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gen_netlist(node.v, wires, insts)
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# create instance
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insts.append(node)
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elif isinstance(node, NotBit):
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# create output wire
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node.wire = 'winv%d' % len(wires)
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wires.append(node.wire)
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# recurse
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gen_netlist(node.v, wires, insts)
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# create instance
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insts.append(node)
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elif isinstance(node, BoothNeg):
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# create output wire
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node.wire = 'wboothneg%d' % len(wires)
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wires.append(node.wire)
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# recurse
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for v in node.pat:
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gen_netlist(v, wires, insts)
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# create instance
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insts.append(node)
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elif isinstance(node, BoothProd):
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# create output wire
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node.wire = 'wboothprod%d' % len(wires)
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wires.append(node.wire)
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# recurse
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for v in node.pat:
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gen_netlist(v, wires, insts)
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for v in node.b:
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gen_netlist(v, wires, insts)
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# create instance
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insts.append(node)
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elif isinstance(node, AddBitD):
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# recurse
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gen_netlist(node.v, wires, insts)
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node.wire = node.v.wire + 'd'
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elif isinstance(node, AddBitC):
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# recurse
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gen_netlist(node.v, wires, insts)
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node.wire = node.v.wire + 'c'
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elif isinstance(node, HalfAdd):
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# create output wires
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node.wire = 'wadd%d' % len(wires)
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wires.append(node.wire + 'd')
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wires.append(node.wire + 'c')
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# recurse
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gen_netlist(node.a, wires, insts)
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gen_netlist(node.b, wires, insts)
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# create instance
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insts.append(node)
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elif isinstance(node, FullAdd):
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# create output wires
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node.wire = 'wadd%d' % len(wires)
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wires.append(node.wire + 'd')
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wires.append(node.wire + 'c')
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# recurse
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gen_netlist(node.a, wires, insts)
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gen_netlist(node.b, wires, insts)
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gen_netlist(node.c, wires, insts)
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# create instance
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insts.append(node)
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elif isinstance(node, CarryProp):
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# create output wires
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node.wire = 'wcarry%d' % len(wires)
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wires.append(node.wire + 'g')
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wires.append(node.wire + 'p')
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# recurse
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gen_netlist(node.a, wires, insts)
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gen_netlist(node.b, wires, insts)
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# create instance
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insts.append(node)
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elif isinstance(node, CarryMerge):
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# create output wires
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node.wire = 'wcarry%d' % len(wires)
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wires.append(node.wire + 'g')
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wires.append(node.wire + 'p')
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# recurse
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gen_netlist(node.p0, wires, insts)
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gen_netlist(node.p1, wires, insts)
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# create instance
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insts.append(node)
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elif isinstance(node, CarryEval):
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# create output wire
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node.wire = 'wcarry%d' % len(wires)
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wires.append(node.wire)
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# recurse
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gen_netlist(node.p, wires, insts)
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gen_netlist(node.c, wires, insts)
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# create instance
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insts.append(node)
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else:
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assert False
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def vhdl_inst(node):
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"""Return (name, ports) for a given instance."""
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if isinstance(node, Reg):
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name = 'smul_flipflop'
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ports = ( 'clk', 'clken', node.v.wire, node.wire )
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elif isinstance(node, NotBit):
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name = 'smul_inverter'
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ports = ( node.v.wire, node.wire )
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elif isinstance(node, BoothNeg):
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name = 'smul_booth_neg'
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ports = ( node.pat[0].wire, node.pat[1].wire, node.pat[2].wire,
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node.wire )
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elif isinstance(node, BoothProd):
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name = 'smul_booth_prod'
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ports = ( node.pat[0].wire, node.pat[1].wire, node.pat[2].wire,
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node.b[0].wire, node.b[1].wire,
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node.wire )
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elif isinstance(node, HalfAdd):
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name = 'smul_half_add'
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ports = ( node.a.wire, node.b.wire,
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node.wire + 'd', node.wire + 'c' )
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elif isinstance(node, FullAdd):
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name = 'smul_full_add'
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ports = ( node.a.wire, node.b.wire, node.c.wire,
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node.wire + 'd', node.wire + 'c' )
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elif isinstance(node, CarryProp):
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name = 'smul_carry_prop'
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ports = ( node.a.wire, node.b.wire,
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node.wire + 'g', node.wire + 'p' )
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elif isinstance(node, CarryMerge):
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name = 'smul_carry_merge'
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ports = ( node.p0.wire + 'g', node.p0.wire + 'p',
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node.p1.wire + 'g', node.p1.wire + 'p',
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node.wire + 'g', node.wire + 'p' )
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elif isinstance(node, CarryEval):
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name = 'smul_carry_eval'
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ports = ( node.p.wire + 'g', node.p.wire + 'p', node.c.wire,
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node.wire )
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else:
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assert False
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return (name, ports)
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|
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|
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def vhdl_wire(wire):
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"""Resolve wire to VHDL expression string."""
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|
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if isinstance(wire, ConstBit):
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return "'%d'" % wire.v
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elif isinstance(wire, InBit):
|
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return "%sin(%d)" % (wire.xy, wire.p)
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else:
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assert isinstance(wire, str)
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return wire
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|
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def gen_vhdl_lib():
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"""Generate VHDL code for library components."""
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print """
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--
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-- Flip-flop.
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--
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|
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library ieee;
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use ieee.std_logic_1164.all;
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|
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entity smul_flipflop is
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port (
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clk: in std_ulogic;
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clken: in std_ulogic;
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d: in std_ulogic;
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q: out std_ulogic );
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end entity;
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|
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architecture smul_flipflop_arch of smul_flipflop is
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begin
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process (clk) is
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begin
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if rising_edge(clk) then
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if to_x01(clken) = '1' then
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q <= d;
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end if;
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end if;
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end process;
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end architecture;
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|
|
|
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--
|
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-- Inverter.
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|
--
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|
|
|
library ieee;
|
|
use ieee.std_logic_1164.all;
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|
|
|
entity smul_inverter is
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port (
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d: in std_ulogic;
|
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q: out std_ulogic );
|
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end entity;
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|
|
|
architecture smul_inverter_arch of smul_inverter is
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begin
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q <= not d;
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end architecture;
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|
|
|
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--
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|
-- Half-adder.
|
|
--
|
|
|
|
library ieee;
|
|
use ieee.std_logic_1164.all;
|
|
|
|
entity smul_half_add is
|
|
port (
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x: in std_ulogic;
|
|
y: in std_ulogic;
|
|
d: out std_ulogic;
|
|
c: out std_ulogic );
|
|
end entity;
|
|
|
|
architecture smul_half_add_arch of smul_half_add is
|
|
begin
|
|
d <= x xor y;
|
|
c <= x and y;
|
|
end architecture;
|
|
|
|
|
|
--
|
|
-- Full-adder.
|
|
--
|
|
|
|
library ieee;
|
|
use ieee.std_logic_1164.all;
|
|
|
|
entity smul_full_add is
|
|
port (
|
|
x: in std_ulogic;
|
|
y: in std_ulogic;
|
|
z: in std_ulogic;
|
|
d: out std_ulogic;
|
|
c: out std_ulogic );
|
|
end entity;
|
|
|
|
architecture smul_full_add_arch of smul_full_add is
|
|
begin
|
|
d <= x xor y xor z;
|
|
c <= (x and y) or (y and z) or (x and z);
|
|
end architecture;
|
|
|
|
|
|
--
|
|
-- Booth negative flag.
|
|
--
|
|
|
|
library ieee;
|
|
use ieee.std_logic_1164.all;
|
|
|
|
entity smul_booth_neg is
|
|
port (
|
|
p0: in std_ulogic;
|
|
p1: in std_ulogic;
|
|
p2: in std_ulogic;
|
|
f: out std_ulogic );
|
|
end entity;
|
|
|
|
architecture smul_booth_neg_arch of smul_booth_neg is
|
|
begin
|
|
f <= p2 and ((not p1) or (not p0));
|
|
end architecture;
|
|
|
|
|
|
--
|
|
-- Booth partial product generation.
|
|
--
|
|
|
|
library ieee;
|
|
use ieee.std_logic_1164.all;
|
|
|
|
entity smul_booth_prod is
|
|
port (
|
|
p0: in std_ulogic;
|
|
p1: in std_ulogic;
|
|
p2: in std_ulogic;
|
|
b0: in std_ulogic;
|
|
b1: in std_ulogic;
|
|
y: out std_ulogic );
|
|
end entity;
|
|
|
|
architecture smul_booth_prod_arch of smul_booth_prod is
|
|
begin
|
|
process (p0, p1, p2, b0, b1) is
|
|
variable p: std_ulogic_vector(2 downto 0);
|
|
begin
|
|
p := (p2, p1, p0);
|
|
case p is
|
|
when "000" => y <= '0'; -- factor 0
|
|
when "001" => y <= b1; -- factor 1
|
|
when "010" => y <= b1; -- factor 1
|
|
when "011" => y <= b0; -- factor 2
|
|
when "100" => y <= not b0; -- factor -2
|
|
when "101" => y <= not b1; -- factor -1
|
|
when "110" => y <= not b1; -- factor -1
|
|
when others => y <= '0'; -- factor 0
|
|
end case;
|
|
end process;
|
|
end architecture;
|
|
|
|
|
|
--
|
|
-- Determine carry generate and carry propagate.
|
|
--
|
|
|
|
library ieee;
|
|
use ieee.std_logic_1164.all;
|
|
|
|
entity smul_carry_prop is
|
|
port (
|
|
a: in std_ulogic;
|
|
b: in std_ulogic;
|
|
g: out std_ulogic;
|
|
p: out std_ulogic );
|
|
end entity;
|
|
|
|
architecture smul_carry_prop of smul_carry_prop is
|
|
begin
|
|
g <= a and b;
|
|
p <= a xor b;
|
|
end architecture;
|
|
|
|
|
|
--
|
|
-- Merge two carry propagation trees.
|
|
--
|
|
|
|
library ieee;
|
|
use ieee.std_logic_1164.all;
|
|
|
|
entity smul_carry_merge is
|
|
port (
|
|
g0: in std_ulogic;
|
|
p0: in std_ulogic;
|
|
g1: in std_ulogic;
|
|
p1: in std_ulogic;
|
|
g: out std_ulogic;
|
|
p: out std_ulogic );
|
|
end entity;
|
|
|
|
architecture smul_carry_merge of smul_carry_merge is
|
|
begin
|
|
g <= g1 or (g0 and p1);
|
|
p <= p0 and p1;
|
|
end architecture;
|
|
|
|
|
|
--
|
|
-- Calculate carry-out through a carry propagation tree.
|
|
--
|
|
|
|
library ieee;
|
|
use ieee.std_logic_1164.all;
|
|
|
|
entity smul_carry_eval is
|
|
port (
|
|
g: in std_ulogic;
|
|
p: in std_ulogic;
|
|
cin: in std_ulogic;
|
|
cout: out std_ulogic );
|
|
end entity;
|
|
|
|
architecture smul_carry_eval of smul_carry_eval is
|
|
begin
|
|
cout <= g or (p and cin);
|
|
end architecture;
|
|
"""
|
|
|
|
|
|
def gen_vhdl_mul(xbits, ybits, npipe, wires, insts, outputs):
|
|
"""Generate VHDL code and write to stdout."""
|
|
|
|
# Declaration.
|
|
print """
|
|
---
|
|
--- %(xbits)d x %(ybits)d bit signed multiplier
|
|
---
|
|
--- %(npipe)d cycles pipeline delay
|
|
---
|
|
|
|
library ieee;
|
|
use ieee.std_logic_1164.all;
|
|
|
|
entity smul_%(xbits)d_%(ybits)d is
|
|
port (
|
|
clk: in std_ulogic;
|
|
clken: in std_ulogic;
|
|
xin: in std_logic_vector(%(xleft)d downto 0);
|
|
yin: in std_logic_vector(%(yleft)d downto 0);
|
|
zout: out std_logic_vector(%(zleft)d downto 0) );
|
|
end entity;
|
|
|
|
architecture arch of smul_%(xbits)d_%(ybits)d is
|
|
""" % { 'xbits': xbits, 'ybits': ybits,
|
|
'npipe': npipe,
|
|
'xleft': xbits-1, 'yleft': ybits-1,
|
|
'zleft': xbits+ybits-1 }
|
|
|
|
# Declare signals.
|
|
for w in wires:
|
|
print "signal %s: std_ulogic;" % w
|
|
|
|
# Start architecture body.
|
|
print
|
|
print "begin"
|
|
print
|
|
|
|
# Instantiate components.
|
|
for (i, node) in enumerate(insts):
|
|
(name, ports) = vhdl_inst(node)
|
|
print "u%d: entity work.%s port map (" % (i, name),
|
|
print ", ".join([ vhdl_wire(p) for p in ports ]),
|
|
print ");"
|
|
|
|
print
|
|
|
|
# Drive output signals.
|
|
for (i, wire) in enumerate(outputs):
|
|
print "zout(%d) <= %s;" % (i, vhdl_wire(wire))
|
|
|
|
# End architecture.
|
|
print
|
|
print "end architecture;"
|
|
|
|
|
|
def verilog_wire(wire):
|
|
"""Resolve wire to Verilog expression string."""
|
|
|
|
if isinstance(wire, ConstBit):
|
|
return "1'b%d" % wire.v
|
|
elif isinstance(wire, InBit):
|
|
return "%sin[%d]" % (wire.xy, wire.p)
|
|
else:
|
|
assert isinstance(wire, str)
|
|
return wire
|
|
|
|
|
|
def gen_verilog_lib():
|
|
"""Generate Verilog code for library components."""
|
|
|
|
print """
|
|
// Flip-flop.
|
|
|
|
module smul_flipflop (
|
|
input wire clk,
|
|
input wire clken,
|
|
input wire d,
|
|
output reg q );
|
|
|
|
always @(posedge clk)
|
|
begin
|
|
if (clken)
|
|
q <= d;
|
|
end
|
|
|
|
endmodule
|
|
|
|
|
|
// Inverter.
|
|
|
|
module smul_inverter (
|
|
input wire d,
|
|
output wire q );
|
|
|
|
assign q = ~d;
|
|
|
|
endmodule
|
|
|
|
|
|
// Half-adder.
|
|
|
|
module smul_half_add (
|
|
input wire x,
|
|
input wire y,
|
|
output wire d,
|
|
output wire c );
|
|
|
|
assign d = x ^ y;
|
|
assign c = x & y;
|
|
|
|
endmodule
|
|
|
|
|
|
// Full-adder.
|
|
|
|
module smul_full_add (
|
|
input wire x,
|
|
input wire y,
|
|
input wire z,
|
|
output wire d,
|
|
output wire c );
|
|
|
|
assign d = x ^ y ^ z;
|
|
assign c = (x & y) | (y & z) | (x & z);
|
|
|
|
endmodule
|
|
|
|
|
|
// Booth negative flag.
|
|
|
|
module smul_booth_neg (
|
|
input wire p0,
|
|
input wire p1,
|
|
input wire p2,
|
|
output wire f );
|
|
|
|
assign f = p2 & ((~p1) | (~p0));
|
|
|
|
endmodule
|
|
|
|
|
|
// Booth partial product generator.
|
|
|
|
module smul_booth_prod (
|
|
input wire p0,
|
|
input wire p1,
|
|
input wire p2,
|
|
input wire u0,
|
|
input wire u1,
|
|
output reg y );
|
|
|
|
always @ (*)
|
|
begin
|
|
case ({p2, p1, p0})
|
|
3'b000 : y = 1'b0;
|
|
3'b001 : y = u1;
|
|
3'b010 : y = u1;
|
|
3'b011 : y = u0;
|
|
3'b100 : y = ~u0;
|
|
3'b101 : y = ~u1;
|
|
3'b110 : y = ~u1;
|
|
default : y = 1'b0;
|
|
endcase
|
|
end
|
|
|
|
endmodule
|
|
|
|
|
|
// Deterimine carry generate and carry propagate.
|
|
|
|
module smul_carry_prop (
|
|
input wire a,
|
|
input wire b,
|
|
output wire g,
|
|
output wire p );
|
|
|
|
assign g = a & b;
|
|
assign p = a ^ b;
|
|
|
|
endmodule
|
|
|
|
|
|
// Merge two carry propagation trees.
|
|
|
|
module smul_carry_merge (
|
|
input wire g0,
|
|
input wire p0,
|
|
input wire g1,
|
|
input wire p1,
|
|
output wire g,
|
|
output wire p );
|
|
|
|
assign g = g1 | (g0 & p1);
|
|
assign p = p0 & p1;
|
|
|
|
endmodule
|
|
|
|
|
|
// Calculate carry-out through a carry propagation tree.
|
|
|
|
module smul_carry_eval (
|
|
input wire g,
|
|
input wire p,
|
|
input wire cin,
|
|
output wire cout );
|
|
|
|
assign cout = g | (p & cin);
|
|
|
|
endmodule
|
|
"""
|
|
|
|
|
|
def gen_verilog_mul(xbits, ybits, npipe, wires, insts, outputs):
|
|
"""Generate Verilog code and write to stdout."""
|
|
|
|
# Preamble.
|
|
print """
|
|
/*
|
|
* %(xbits)d x %(ybits)d bit signed multiplier
|
|
*
|
|
* %(npipe)d cycles pipeline delay
|
|
*/
|
|
|
|
module smul_%(xbits)d_%(ybits)d (
|
|
input wire clk,
|
|
input wire clken,
|
|
input wire [%(xleft)d:0] xin,
|
|
input wire [%(yleft)d:0] yin,
|
|
output wire [%(zleft)d:0] zout );
|
|
""" % { 'xbits': xbits, 'ybits': ybits,
|
|
'npipe': npipe,
|
|
'xleft': xbits-1, 'yleft': ybits-1,
|
|
'zleft': xbits+ybits-1 }
|
|
|
|
# Declare signals.
|
|
for w in wires:
|
|
print "wire %s;" % w
|
|
|
|
# Instantiate components.
|
|
for (i, node) in enumerate(insts):
|
|
(name, ports) = vhdl_inst(node)
|
|
print "%s u%d (" % (name, i),
|
|
print ", ".join([ verilog_wire(p) for p in ports ]),
|
|
print ");"
|
|
|
|
print
|
|
|
|
# Drive output signals.
|
|
for (i, wire) in enumerate(outputs):
|
|
print "assign zout[%d] = %s;" % (i, verilog_wire(wire))
|
|
|
|
# End module.
|
|
print
|
|
print "endmodule"
|
|
|
|
|
|
def main():
|
|
|
|
parser = argparse.ArgumentParser()
|
|
parser.format_help = lambda: __doc__
|
|
parser.format_usage = lambda: __doc__
|
|
|
|
parser.add_argument('--lang', action='store', type=str)
|
|
parser.add_argument('--nolib', action='store_true', default=False)
|
|
parser.add_argument('--lib', action='store_true', default=False)
|
|
parser.add_argument('Xbits', action='store', type=int, nargs='?')
|
|
parser.add_argument('Ybits', action='store', type=int, nargs='?')
|
|
parser.add_argument('npipe', action='store', type=int, nargs='?')
|
|
|
|
args = parser.parse_args()
|
|
|
|
if args.lang is None or args.lang.upper() not in ('VHDL', 'VERILOG'):
|
|
print >>sys.stderr, __doc__
|
|
print >>sys.stderr, "ERROR: Must specify --lang=vhdl or --lang=verilog"
|
|
sys.exit(1)
|
|
|
|
if args.lib:
|
|
if (args.nolib or
|
|
args.Xbits is not None or
|
|
args.Ybits is not None or
|
|
args.npipe is not None):
|
|
print >>sys.stderr, __doc__
|
|
print >>sys.stderr, "ERROR: Must specify either --lib or",
|
|
print >>sys.stderr, "Xbits, Ybits, npipe"
|
|
sys.exit(1)
|
|
else:
|
|
if (args.Xbits is None or args.Ybits is None or args.npipe is None):
|
|
print >>sys.stderr, __doc__
|
|
print >>sys.stderr, "ERROR: Must specify either --lib or",
|
|
print >>sys.stderr, "Xbits, Ybits, npipe"
|
|
sys.exit(1)
|
|
|
|
if args.Xbits < 4 or args.Ybits < args.Xbits:
|
|
print >>sys.stderr, "ERROR: invalid word lengths"
|
|
sys.exit(1)
|
|
|
|
if args.npipe < 0 or args.npipe > 2:
|
|
print >>sys.stderr, "ERROR: invalid number of register stages"
|
|
sys.exit(1)
|
|
|
|
if not args.lib:
|
|
# Generate expression tree.
|
|
zvec = gen_multiplier(args.Xbits, args.Ybits, args.npipe)
|
|
|
|
# Generate wires and instances.
|
|
wires = [ ]
|
|
insts = [ ]
|
|
for node in zvec:
|
|
gen_netlist(node, wires, insts)
|
|
outputs = [ node.wire for node in zvec ]
|
|
|
|
# Write library components.
|
|
if not args.nolib:
|
|
if args.lang.upper() == 'VHDL':
|
|
gen_vhdl_lib()
|
|
elif args.lang.upper() == 'VERILOG':
|
|
gen_verilog_lib()
|
|
|
|
# Write multiplier.
|
|
if not args.lib:
|
|
if args.lang.upper() == 'VHDL':
|
|
gen_vhdl_mul(args.Xbits, args.Ybits, args.npipe,
|
|
wires, insts, outputs)
|
|
elif args.lang.upper() == 'VERILOG':
|
|
gen_verilog_mul(args.Xbits, args.Ybits, args.npipe,
|
|
wires, insts, outputs)
|
|
|
|
|
|
if __name__ == '__main__':
|
|
main()
|
|
|
|
# end
|