Signed multiplier in VHDL or Verilog

Joris van Rantwijk 623c0a7d9c Move example to subdirectory and put library components in separate file.		2016-03-07 22:03:37 +01:00
example	Move example to subdirectory and put library components in separate file.	2016-03-07 22:03:37 +01:00
vhdl_sim	Add VHDL testbench and makefile for simulation with GHDL.	2016-03-07 21:59:26 +01:00
genmul.py	Python script to generate multiplier code.	2016-03-07 21:55:26 +01:00