Joris van Rantwijk 73c857b92d Add VHDL testbench and makefile for simulation with GHDL.		2016-03-07 21:59:26 +01:00
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Makefile	Add VHDL testbench and makefile for simulation with GHDL.	2016-03-07 21:59:26 +01:00
tb.vhdl	Add VHDL testbench and makefile for simulation with GHDL.	2016-03-07 21:59:26 +01:00