230 lines
6.9 KiB
VHDL
230 lines
6.9 KiB
VHDL
--
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-- Test bench for signed multiplier.
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--
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity tb is
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end entity;
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architecture arch of tb is
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procedure test_mul(constant xbits: in integer;
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constant ybits: in integer;
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constant npipe: in integer;
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signal clk: out std_ulogic;
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signal xin: out std_logic_vector;
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signal yin: out std_logic_vector;
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signal zout: in std_logic_vector) is
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variable all_x: boolean;
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variable all_y: boolean;
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variable num_x: integer;
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variable num_y: integer;
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variable x: integer;
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variable y: integer;
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variable i: integer;
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type pipe_type is array (0 to npipe) of integer;
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variable px, py: pipe_type;
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begin
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-- Test all X inputs if xbits <= 11; otherwise test a subset.
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all_x := (xbits <= 11);
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if all_x then
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num_x := 2**xbits;
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else
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num_x := (xbits-8) * 2 * 256;
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end if;
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-- Test all Y inputs if ybits <= 11; otherwise test a subset.
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all_y := (ybits <= 11);
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if all_y then
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num_y := 2**ybits;
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else
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num_y := (ybits-8) * 2 * 256;
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end if;
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i := 0;
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for kx in 0 to num_x-1 loop
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if all_x then
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x := kx - 2**(xbits-1);
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else
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x := (kx mod 512 - 256) * 2**(kx/512);
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end if;
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for ky in 0 to num_y-1 loop
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if all_y then
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y := ky - 2**(ybits-1);
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else
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y := (ky mod 512 - 256) * (2**(ky/512));
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end if;
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clk <= '0';
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xin <= std_logic_vector(to_signed(x, xbits));
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yin <= std_logic_vector(to_signed(y, ybits));
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wait for 5 ns;
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px(1 to npipe) := px(0 to npipe-1);
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py(1 to npipe) := py(0 to npipe-1);
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px(0) := x;
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py(0) := y;
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if i >= npipe then
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assert zout =
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std_logic_vector(to_signed(px(npipe), xbits) *
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to_signed(py(npipe), ybits));
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end if;
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clk <= '1';
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wait for 5 ns;
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i := i + 1;
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end loop;
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end loop;
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xin(xin'high downto xin'low) <= (others => 'U');
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yin(yin'high downto yin'low) <= (others => 'U');
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for i in 1 to npipe loop
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px(1 to npipe) := px(0 to npipe-1);
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py(1 to npipe) := py(0 to npipe-1);
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assert zout = std_logic_vector(to_signed(px(npipe), xbits) *
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to_signed(py(npipe), ybits));
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clk <= '0';
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wait for 5 ns;
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clk <= '1';
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wait for 5 ns;
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end loop;
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clk <= '0';
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end procedure;
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signal s1_clk: std_ulogic;
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signal s1_xin: std_logic_vector(3 downto 0);
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signal s1_yin: std_logic_vector(3 downto 0);
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signal s1_zout: std_logic_vector(7 downto 0);
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signal s2_clk: std_ulogic;
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signal s2_xin: std_logic_vector(6 downto 0);
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signal s2_yin: std_logic_vector(7 downto 0);
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signal s2_zout: std_logic_vector(14 downto 0);
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signal s3_clk: std_ulogic;
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signal s3_xin: std_logic_vector(7 downto 0);
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signal s3_yin: std_logic_vector(7 downto 0);
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signal s3_zout: std_logic_vector(15 downto 0);
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signal s4_clk: std_ulogic;
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signal s4_xin: std_logic_vector(9 downto 0);
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signal s4_yin: std_logic_vector(10 downto 0);
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signal s4_zout: std_logic_vector(20 downto 0);
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signal s5_clk: std_ulogic;
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signal s5_xin: std_logic_vector(3 downto 0);
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signal s5_yin: std_logic_vector(11 downto 0);
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signal s5_zout: std_logic_vector(15 downto 0);
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signal s6_clk: std_ulogic;
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signal s6_xin: std_logic_vector(17 downto 0);
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signal s6_yin: std_logic_vector(17 downto 0);
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signal s6_zout: std_logic_vector(35 downto 0);
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signal s7_clk: std_ulogic;
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signal s7_xin: std_logic_vector(18 downto 0);
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signal s7_yin: std_logic_vector(23 downto 0);
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signal s7_zout: std_logic_vector(42 downto 0);
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begin
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-- Signed 4x4 multiplier, latency 0 clocks.
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u1: entity work.smul_4_4
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port map ( clk => s1_clk,
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clken => '1',
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xin => s1_xin,
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yin => s1_yin,
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zout => s1_zout );
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-- Signed 7x8 multiplier, latency 0 clocks.
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u2: entity work.smul_7_8
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port map ( clk => s2_clk,
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clken => '1',
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xin => s2_xin,
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yin => s2_yin,
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zout => s2_zout );
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-- Signex 8x8 multiplier, latency 0 clocks.
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u3: entity work.smul_8_8
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port map ( clk => s3_clk,
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clken => '1',
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xin => s3_xin,
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yin => s3_yin,
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zout => s3_zout );
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-- Signex 10x11 multiplier, latency 0 clocks.
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u4: entity work.smul_10_11
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port map ( clk => s4_clk,
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clken => '1',
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xin => s4_xin,
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yin => s4_yin,
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zout => s4_zout );
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-- Signex 4x12 multiplier, latency 1 clock.
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u5: entity work.smul_4_12
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port map ( clk => s5_clk,
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clken => '1',
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xin => s5_xin,
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yin => s5_yin,
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zout => s5_zout );
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-- Signex 18x18 multiplier, latency 2 clocks.
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u6: entity work.smul_18_18
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port map ( clk => s6_clk,
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clken => '1',
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xin => s6_xin,
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yin => s6_yin,
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zout => s6_zout );
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-- Signex 19x24 multiplier, latency 1 clock.
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u7: entity work.smul_19_24
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port map ( clk => s7_clk,
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clken => '1',
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xin => s7_xin,
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yin => s7_yin,
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zout => s7_zout );
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process is
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begin
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report "Start test bench";
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report "Testing 4x4 multiplier, latency 0";
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test_mul(4, 4, 0, s1_clk, s1_xin, s1_yin, s1_zout);
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report "Testing 7x8 multiplier, latency 0";
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test_mul(7, 8, 0, s2_clk, s2_xin, s2_yin, s2_zout);
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report "Testing 8x8 multiplier, latency 0";
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test_mul(8, 8, 0, s3_clk, s3_xin, s3_yin, s3_zout);
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report "Testing 10x11 multiplier, latency 0";
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test_mul(10, 11, 0, s4_clk, s4_xin, s4_yin, s4_zout);
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report "Testing 4x12 multiplier, latency 1 (subset of inputs)";
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test_mul(4, 12, 1, s5_clk, s5_xin, s5_yin, s5_zout);
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report "Testing 18x18 multiplier, latency 2 (subset of inputs)";
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test_mul(18, 18, 2, s6_clk, s6_xin, s6_yin, s6_zout);
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report "Testing 19x24 multiplier, latency 1 (subset of inputs)";
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test_mul(19, 24, 1, s7_clk, s7_xin, s7_yin, s7_zout);
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report "End test bench";
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wait;
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end process;
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end architecture;
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