Move example to subdirectory and put library components in separate file.
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--
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-- Flip-flop.
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--
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library ieee;
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use ieee.std_logic_1164.all;
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entity smul_flipflop is
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port (
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clk: in std_ulogic;
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clken: in std_ulogic;
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d: in std_ulogic;
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q: out std_ulogic );
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end entity;
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architecture smul_flipflop_arch of smul_flipflop is
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begin
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process (clk) is
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begin
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if rising_edge(clk) then
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if to_x01(clken) = '1' then
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q <= d;
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end if;
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end if;
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end process;
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end architecture;
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--
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-- Inverter.
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--
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library ieee;
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use ieee.std_logic_1164.all;
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entity smul_inverter is
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port (
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d: in std_ulogic;
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q: out std_ulogic );
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end entity;
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architecture smul_inverter_arch of smul_inverter is
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begin
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q <= not d;
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end architecture;
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--
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-- Half-adder.
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--
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library ieee;
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use ieee.std_logic_1164.all;
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entity smul_half_add is
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port (
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x: in std_ulogic;
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y: in std_ulogic;
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d: out std_ulogic;
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c: out std_ulogic );
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end entity;
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architecture smul_half_add_arch of smul_half_add is
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begin
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d <= x xor y;
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c <= x and y;
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end architecture;
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--
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-- Full-adder.
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--
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library ieee;
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use ieee.std_logic_1164.all;
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entity smul_full_add is
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port (
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x: in std_ulogic;
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y: in std_ulogic;
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z: in std_ulogic;
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d: out std_ulogic;
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c: out std_ulogic );
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end entity;
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architecture smul_full_add_arch of smul_full_add is
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begin
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d <= x xor y xor z;
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c <= (x and y) or (y and z) or (x and z);
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end architecture;
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--
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-- Booth negative flag.
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--
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library ieee;
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use ieee.std_logic_1164.all;
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entity smul_booth_neg is
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port (
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p0: in std_ulogic;
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p1: in std_ulogic;
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p2: in std_ulogic;
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f: out std_ulogic );
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end entity;
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architecture smul_booth_neg_arch of smul_booth_neg is
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begin
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f <= p2 and ((not p1) or (not p0));
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end architecture;
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--
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-- Booth partial product generation.
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--
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library ieee;
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use ieee.std_logic_1164.all;
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entity smul_booth_prod is
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port (
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p0: in std_ulogic;
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p1: in std_ulogic;
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p2: in std_ulogic;
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b0: in std_ulogic;
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b1: in std_ulogic;
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y: out std_ulogic );
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end entity;
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architecture smul_booth_prod_arch of smul_booth_prod is
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begin
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process (p0, p1, p2, b0, b1) is
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variable p: std_ulogic_vector(2 downto 0);
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begin
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p := (p2, p1, p0);
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case p is
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when "000" => y <= '0'; -- factor 0
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when "001" => y <= b1; -- factor 1
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when "010" => y <= b1; -- factor 1
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when "011" => y <= b0; -- factor 2
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when "100" => y <= not b0; -- factor -2
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when "101" => y <= not b1; -- factor -1
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when "110" => y <= not b1; -- factor -1
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when others => y <= '0'; -- factor 0
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end case;
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end process;
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end architecture;
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--
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-- Determine carry generate and carry propagate.
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--
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library ieee;
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use ieee.std_logic_1164.all;
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entity smul_carry_prop is
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port (
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a: in std_ulogic;
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b: in std_ulogic;
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g: out std_ulogic;
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p: out std_ulogic );
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end entity;
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architecture smul_carry_prop of smul_carry_prop is
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begin
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g <= a and b;
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p <= a xor b;
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end architecture;
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--
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-- Merge two carry propagation trees.
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--
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library ieee;
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use ieee.std_logic_1164.all;
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entity smul_carry_merge is
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port (
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g0: in std_ulogic;
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p0: in std_ulogic;
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g1: in std_ulogic;
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p1: in std_ulogic;
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g: out std_ulogic;
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p: out std_ulogic );
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end entity;
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architecture smul_carry_merge of smul_carry_merge is
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begin
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g <= g1 or (g0 and p1);
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p <= p0 and p1;
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end architecture;
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--
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-- Calculate carry-out through a carry propagation tree.
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--
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library ieee;
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use ieee.std_logic_1164.all;
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entity smul_carry_eval is
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port (
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g: in std_ulogic;
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p: in std_ulogic;
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cin: in std_ulogic;
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cout: out std_ulogic );
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end entity;
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architecture smul_carry_eval of smul_carry_eval is
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begin
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cout <= g or (p and cin);
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end architecture;
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---
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--- 8 x 8 bit signed multiplier
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---
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@ -0,0 +1,217 @@
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--
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-- Flip-flop.
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--
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library ieee;
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use ieee.std_logic_1164.all;
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entity smul_flipflop is
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port (
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clk: in std_ulogic;
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clken: in std_ulogic;
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d: in std_ulogic;
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q: out std_ulogic );
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end entity;
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architecture smul_flipflop_arch of smul_flipflop is
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begin
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process (clk) is
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begin
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if rising_edge(clk) then
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if to_x01(clken) = '1' then
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q <= d;
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end if;
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end if;
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end process;
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end architecture;
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--
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-- Inverter.
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--
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library ieee;
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use ieee.std_logic_1164.all;
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entity smul_inverter is
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port (
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d: in std_ulogic;
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q: out std_ulogic );
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end entity;
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architecture smul_inverter_arch of smul_inverter is
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begin
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q <= not d;
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end architecture;
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--
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-- Half-adder.
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--
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library ieee;
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use ieee.std_logic_1164.all;
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entity smul_half_add is
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port (
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x: in std_ulogic;
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y: in std_ulogic;
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d: out std_ulogic;
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c: out std_ulogic );
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end entity;
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architecture smul_half_add_arch of smul_half_add is
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begin
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d <= x xor y;
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c <= x and y;
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end architecture;
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--
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-- Full-adder.
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--
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library ieee;
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use ieee.std_logic_1164.all;
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entity smul_full_add is
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port (
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x: in std_ulogic;
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y: in std_ulogic;
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z: in std_ulogic;
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d: out std_ulogic;
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c: out std_ulogic );
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end entity;
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architecture smul_full_add_arch of smul_full_add is
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begin
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d <= x xor y xor z;
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c <= (x and y) or (y and z) or (x and z);
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end architecture;
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--
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-- Booth negative flag.
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--
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library ieee;
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use ieee.std_logic_1164.all;
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entity smul_booth_neg is
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port (
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p0: in std_ulogic;
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p1: in std_ulogic;
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p2: in std_ulogic;
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f: out std_ulogic );
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end entity;
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architecture smul_booth_neg_arch of smul_booth_neg is
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begin
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f <= p2 and ((not p1) or (not p0));
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end architecture;
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--
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-- Booth partial product generation.
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--
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library ieee;
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use ieee.std_logic_1164.all;
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entity smul_booth_prod is
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port (
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p0: in std_ulogic;
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p1: in std_ulogic;
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p2: in std_ulogic;
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b0: in std_ulogic;
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b1: in std_ulogic;
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y: out std_ulogic );
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end entity;
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architecture smul_booth_prod_arch of smul_booth_prod is
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begin
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process (p0, p1, p2, b0, b1) is
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variable p: std_ulogic_vector(2 downto 0);
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begin
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p := (p2, p1, p0);
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case p is
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when "000" => y <= '0'; -- factor 0
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when "001" => y <= b1; -- factor 1
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when "010" => y <= b1; -- factor 1
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when "011" => y <= b0; -- factor 2
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when "100" => y <= not b0; -- factor -2
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when "101" => y <= not b1; -- factor -1
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when "110" => y <= not b1; -- factor -1
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when others => y <= '0'; -- factor 0
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end case;
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end process;
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end architecture;
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--
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-- Determine carry generate and carry propagate.
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--
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library ieee;
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use ieee.std_logic_1164.all;
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entity smul_carry_prop is
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port (
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a: in std_ulogic;
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b: in std_ulogic;
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g: out std_ulogic;
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p: out std_ulogic );
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end entity;
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architecture smul_carry_prop of smul_carry_prop is
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begin
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g <= a and b;
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p <= a xor b;
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end architecture;
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--
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-- Merge two carry propagation trees.
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--
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library ieee;
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use ieee.std_logic_1164.all;
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entity smul_carry_merge is
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port (
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g0: in std_ulogic;
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p0: in std_ulogic;
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g1: in std_ulogic;
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p1: in std_ulogic;
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g: out std_ulogic;
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p: out std_ulogic );
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end entity;
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architecture smul_carry_merge of smul_carry_merge is
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begin
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g <= g1 or (g0 and p1);
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p <= p0 and p1;
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end architecture;
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--
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-- Calculate carry-out through a carry propagation tree.
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--
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library ieee;
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use ieee.std_logic_1164.all;
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entity smul_carry_eval is
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port (
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g: in std_ulogic;
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p: in std_ulogic;
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cin: in std_ulogic;
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cout: out std_ulogic );
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end entity;
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architecture smul_carry_eval of smul_carry_eval is
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begin
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cout <= g or (p and cin);
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end architecture;
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