joris
/
hdl-multiplier
1
0
Fork 0
Code Issues Pull Requests Projects Releases Wiki Activity

Remove reference to unavailable paper.

This commit is contained in:
Joris van Rantwijk 2016-03-08 08:01:20 +01:00
parent 623c0a7d9c
commit 3feadedad7
1 changed files with 6 additions and 8 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
genmul.py
View File

@ -12,13 +12,11 @@ Usage: genmul.py --lang=vhdl|verilog --lib
npipe Number of register stages (0 or 1 or 2) npipe Number of register stages (0 or 1 or 2)
See also: See also:
G. Knagge, "ASIC Design for Signal Processing", G. Knagge, "ASIC Design for Signal Processing",
http://www.geoffknagge.com/fyp/booth.shtml, 2010. http://www.geoffknagge.com/fyp/booth.shtml, 2010.
X. Xiong, M. Lin, "Low Power 8-bit Baugh-Wooley Multiplier Based on Wallace L. Dadda, "Some schemes for parallel multipliers",
Tree Architecture", Lecture Notes in Electrical Engineering, 2012.
L. Dadda, "Some schemes for parallel multipliers",
Associazione Elettrotecnica et Elettronica Italiana, 1965. Associazione Elettrotecnica et Elettronica Italiana, 1965.
R. P. Brent, H. T. Kung, "A Regular Layout for Parallel Adders", R. P. Brent, H. T. Kung, "A Regular Layout for Parallel Adders",
IEEE Transactions on Computers, 1982. IEEE Transactions on Computers, 1982.
""" """