From 3feadedad7b67a9a1d32769a63efdba8d00dd3a5 Mon Sep 17 00:00:00 2001 From: Joris van Rantwijk Date: Tue, 8 Mar 2016 08:01:20 +0100 Subject: [PATCH] Remove reference to unavailable paper. --- genmul.py | 14 ++++++-------- 1 file changed, 6 insertions(+), 8 deletions(-) diff --git a/genmul.py b/genmul.py index 7c7be2f..03be6ce 100644 --- a/genmul.py +++ b/genmul.py @@ -12,14 +12,12 @@ Usage: genmul.py --lang=vhdl|verilog --lib npipe Number of register stages (0 or 1 or 2) See also: -G. Knagge, "ASIC Design for Signal Processing", - http://www.geoffknagge.com/fyp/booth.shtml, 2010. -X. Xiong, M. Lin, "Low Power 8-bit Baugh-Wooley Multiplier Based on Wallace - Tree Architecture", Lecture Notes in Electrical Engineering, 2012. -L. Dadda, "Some schemes for parallel multipliers", - Associazione Elettrotecnica et Elettronica Italiana, 1965. -R. P. Brent, H. T. Kung, "A Regular Layout for Parallel Adders", - IEEE Transactions on Computers, 1982. + G. Knagge, "ASIC Design for Signal Processing", + http://www.geoffknagge.com/fyp/booth.shtml, 2010. + L. Dadda, "Some schemes for parallel multipliers", + Associazione Elettrotecnica et Elettronica Italiana, 1965. + R. P. Brent, H. T. Kung, "A Regular Layout for Parallel Adders", + IEEE Transactions on Computers, 1982. """ import sys