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vhdl-sincos-gen
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22 Commits

Author SHA1 Message Date
Joris van Rantwijk 5e02c373de * Implement serial port interface in test design. 2016-04-18 21:14:31 +02:00
Joris van Rantwijk 5b72e7f3f3 * Start work on synthesizable tester for sin/cos core. 2016-04-16 22:56:42 +02:00
Joris van Rantwijk cf4e802edf * Add comment in simulation Makefile. 2016-04-16 22:18:41 +02:00
Joris van Rantwijk 5892955445 * Reorganize comments at top of wrappers for sin/cos generator. 2016-04-16 22:16:20 +02:00
Joris van Rantwijk 8796491f37 * Further reduction of multiplier width. 
At this point it very slightly affects output quality.
  This change makes it possible to implement up to 24-bit sine generators
  using just 18x18-bit multipliers (i.e. Spartan-6).
 2016-04-16 09:10:27 +02:00
Joris van Rantwijk 7ce5b82ff0 * eval_sine_quality.py: Add Python program to evaluate sine waveform. 2016-04-16 09:09:28 +02:00
Joris van Rantwijk aa8f0217d3 * Full (all-input) test bench for sincos_gen_d18_p20. 2016-04-14 23:56:19 +02:00
Joris van Rantwijk d2a948f34e * Fix mistake in 2nd order Taylor correction. 
* Fix mistake in testbench for 24-bit sine generator.
 2016-04-14 23:14:58 +02:00
Joris van Rantwijk 15518ce6f7 * Add test-bench for superficial check of 24-bit sine generator. 
* Minor improvement in test-bench for 18-bit sine generator.
 2016-04-14 23:06:21 +02:00
Joris van Rantwijk 42046dc818 * Add wrapper for 24-bit sine generator. 2016-04-14 22:53:40 +02:00
Joris van Rantwijk 9873f91e8e * Further reduction of multiplier width. 
* Add more comments.
 2016-04-14 22:49:32 +02:00
Joris van Rantwijk a3d8939440 * Add comments. 2016-04-14 00:42:58 +02:00
Joris van Rantwijk 2dbc6d44db * Reduce width of sin/cos input to multiplier by 1 bit. 
* This has no significant effect on accuracy, but reduces multiplier width.
 2016-04-14 00:05:52 +02:00
Joris van Rantwijk 9f4bb7f9b0 * Increase precision of delta_phase term by 1 bit. 
* This improves accuracy of 1st order Taylor variant to less than 1.0 lsb peak deviation.
* Add comments.
 2016-04-13 23:32:02 +02:00
Joris van Rantwijk 12b896c2df Fix mistake in Taylor correction. 
This improves accuracy, but there is probably room for further improvement by avoiding accumulation of rounding errors.
 2016-04-11 23:21:25 +02:00
Joris van Rantwijk 7de76c6696 Reduce amplitude to avoid numeric overflow. 2016-04-11 21:28:17 +02:00
Joris van Rantwijk 0685db9d92 Document latency of sincos core. 2016-04-10 01:27:24 +02:00
Joris van Rantwijk e8fdb3cff1 Full (all-input) test bench for sincos_gen_d18_p20. 2016-04-10 01:26:05 +02:00
Joris van Rantwijk 7703971a4d Add Makefile for simulation with GHDL. 2016-03-24 23:55:32 +01:00
Joris van Rantwijk e078fffd3e Test bench for sincos_gen_d18_p20. 2016-03-24 23:37:00 +01:00
Joris van Rantwijk 8090886ab0 VHDL wrapper for sin/cos function with 18-bit sin/cos, 20-bit phase. 2016-03-24 23:34:20 +01:00
Joris van Rantwijk 59ec0505ab Main VHDL file of sin/cos function core. 2016-03-24 23:32:59 +01:00