 Joris van Rantwijk
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15518ce6f7
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* Add test-bench for superficial check of 24-bit sine generator.
* Minor improvement in test-bench for 18-bit sine generator.
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2016-04-14 23:06:21 +02:00 |
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Joris van Rantwijk
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42046dc818
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* Add wrapper for 24-bit sine generator.
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2016-04-14 22:53:40 +02:00 |
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Joris van Rantwijk
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9873f91e8e
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* Further reduction of multiplier width.
* Add more comments.
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2016-04-14 22:49:32 +02:00 |
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Joris van Rantwijk
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a3d8939440
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* Add comments.
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2016-04-14 00:42:58 +02:00 |
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Joris van Rantwijk
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2dbc6d44db
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* Reduce width of sin/cos input to multiplier by 1 bit.
* This has no significant effect on accuracy, but reduces multiplier width.
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2016-04-14 00:05:52 +02:00 |
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Joris van Rantwijk
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9f4bb7f9b0
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* Increase precision of delta_phase term by 1 bit.
* This improves accuracy of 1st order Taylor variant to less than 1.0 lsb peak deviation.
* Add comments.
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2016-04-13 23:32:02 +02:00 |
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Joris van Rantwijk
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12b896c2df
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Fix mistake in Taylor correction.
This improves accuracy, but there is probably room for further improvement by avoiding accumulation of rounding errors.
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2016-04-11 23:21:25 +02:00 |
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Joris van Rantwijk
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7de76c6696
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Reduce amplitude to avoid numeric overflow.
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2016-04-11 21:28:17 +02:00 |
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Joris van Rantwijk
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0685db9d92
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Document latency of sincos core.
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2016-04-10 01:27:24 +02:00 |
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Joris van Rantwijk
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e8fdb3cff1
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Full (all-input) test bench for sincos_gen_d18_p20.
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2016-04-10 01:26:05 +02:00 |
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Joris van Rantwijk
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7703971a4d
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Add Makefile for simulation with GHDL.
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2016-03-24 23:55:32 +01:00 |
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Joris van Rantwijk
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e078fffd3e
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Test bench for sincos_gen_d18_p20.
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2016-03-24 23:37:00 +01:00 |
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Joris van Rantwijk
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8090886ab0
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VHDL wrapper for sin/cos function with 18-bit sin/cos, 20-bit phase.
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2016-03-24 23:34:20 +01:00 |
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Joris van Rantwijk
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59ec0505ab
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Main VHDL file of sin/cos function core.
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2016-03-24 23:32:59 +01:00 |