119 lines
2.9 KiB
VHDL
119 lines
2.9 KiB
VHDL
--
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-- Test bench for PRNG "xoroshiro128+".
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--
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity tb_xoroshiro128plus is
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end entity;
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architecture arch of tb_xoroshiro128plus is
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signal clk: std_logic;
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signal clock_active: boolean := false;
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signal s_rst: std_logic;
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signal s_enable: std_logic;
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signal s_reseed: std_logic;
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signal s_newseed: std_logic_vector(127 downto 0);
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signal s_output: std_logic_vector(63 downto 0);
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function to_hex_string(s: std_logic_vector)
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return string
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is
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constant alphabet: string(1 to 16) := "0123456789abcdef";
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variable y: string(1 to s'length/4);
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begin
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for i in y'range loop
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y(i) := alphabet(to_integer(unsigned(s(s'high+4-4*i downto s'high+1-4*i))) + 1);
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end loop;
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return y;
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end function;
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begin
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-- Instantiate PRNG.
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inst_prng: entity work.xoroshiro128plus
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generic map (
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init_seed => x"0123456789abcdef3141592653589793" )
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port map (
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clk => clk,
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rst => s_rst,
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enable => s_enable,
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reseed => s_reseed,
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newseed => s_newseed,
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output => s_output );
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-- Generate clock.
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clk <= (not clk) after 10 ns when clock_active else '0';
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-- Main simulation process.
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process is
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begin
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report "Start test bench";
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-- Reset.
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s_rst <= '1';
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s_enable <= '0';
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s_reseed <= '0';
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s_newseed <= (others => '0');
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-- Start clock.
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clock_active <= true;
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-- Wait 2 clock cycles, then end reset.
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wait for 30 ns;
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wait until falling_edge(clk);
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s_rst <= '0';
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-- Produce numbers
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for i in 0 to 150 loop
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if i mod 5 = 0 or i mod 7 = 0 then
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s_enable <= '0';
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wait until falling_edge(clk);
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else
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s_enable <= '1';
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wait until falling_edge(clk);
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report "Got 0x" & to_hex_string(s_output);
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end if;
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end loop;
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-- Re-seed generator.
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report "Re-seed generator";
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s_enable <= '1';
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s_reseed <= '1';
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s_newseed <= x"3141592653589793fedcba9876543210";
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wait until falling_edge(clk);
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s_reseed <= '0';
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s_newseed <= (others => '0');
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-- Produce numbers
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for i in 0 to 150 loop
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if i mod 5 = 0 or i mod 7 = 0 then
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s_enable <= '0';
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wait until falling_edge(clk);
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else
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s_enable <= '1';
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wait until falling_edge(clk);
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report "Got 0x" & to_hex_string(s_output);
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end if;
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end loop;
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-- End simulation.
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report "End testbench";
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clock_active <= false;
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wait;
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end process;
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end architecture;
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