vhdl-prng/rtl
Joris van Rantwijk 9f5c69c9cc Add optional pipeline stage in xoshiro128++ 2020-08-14 11:48:26 +02:00
..
rng_mt19937.vhdl Set initial values for signals. 2016-11-20 21:19:23 +01:00
rng_trivium.vhdl Trivium: Flip bit-order. 2016-11-24 00:23:35 +01:00
rng_xoroshiro128plus.vhdl Update xoroshiro128+ to 1.0 version 2020-08-11 18:13:48 +02:00
rng_xoshiro128plusplus.vhdl Add optional pipeline stage in xoshiro128++ 2020-08-14 11:48:26 +02:00