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Pseudo-Random Number Generators in VHDL
6 Commits 1 Branch 0 Tags 84 KiB
VHDL 82.1%
C 8.3%
C++ 7.7%
Makefile 1.9%
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Joris van Rantwijk 404c307f62 Test bench for Xoroshiro128plus: 
* Update tb_xoroshiro128plus for new interface.
 * Add Makefile for testbenches with GHDL.
 		2016-10-21 13:54:42 +02:00
refimpl Test bench for Xoroshiro128plus: 2016-10-21 13:54:42 +02:00
rtl Rename entity xoroshiro128 and change interface. 2016-10-21 13:12:02 +02:00
sim Test bench for Xoroshiro128plus: 2016-10-21 13:54:42 +02:00