Rename entity xoroshiro128 and change interface.

* Rename to rng_xoroshiro128plus
 * Change interface to valid/ready-based stream (not tested).
This commit is contained in:
Joris van Rantwijk 2016-10-21 13:12:02 +02:00
parent 8642b7291e
commit b498a1e543
1 changed files with 31 additions and 19 deletions

View File

@ -4,7 +4,7 @@
-- Author: Joris van Rantwijk <joris@jorisvr.nl> -- Author: Joris van Rantwijk <joris@jorisvr.nl>
-- --
-- This is a 64-bit random number generator in synthesizable VHDL. -- This is a 64-bit random number generator in synthesizable VHDL.
-- The generator produces 64 new random bits on every (enabled) clock cycle. -- The generator can produce 64 new random bits on every clock cycle.
-- --
-- The algorithm "xoroshiro128+" is by David Blackman and Sebastiano Vigna. -- The algorithm "xoroshiro128+" is by David Blackman and Sebastiano Vigna.
-- See also http://xoroshiro.di.unimi.it/ -- See also http://xoroshiro.di.unimi.it/
@ -14,8 +14,8 @@
-- to initialize the generator at reset. The generator also supports -- to initialize the generator at reset. The generator also supports
-- re-seeding at run time. -- re-seeding at run time.
-- --
-- After reset, at least one clock cycle is needed before valid -- After reset and after re-seeding, at least one clock cycle is needed
-- random data appears on the output. -- before valid random data appears on the output.
-- --
-- NOTE: This is not a cryptographic random number generator. -- NOTE: This is not a cryptographic random number generator.
-- --
@ -39,7 +39,7 @@ use ieee.std_logic_1164.all;
use ieee.numeric_std.all; use ieee.numeric_std.all;
entity xoroshiro128plus is entity rng_xoroshiro128plus is
generic ( generic (
-- Default seed value. -- Default seed value.
@ -53,29 +53,37 @@ entity xoroshiro128plus is
-- Synchronous reset, active high. -- Synchronous reset, active high.
rst: in std_logic; rst: in std_logic;
-- Clock enable, active high. -- High to request re-seeding of the generator.
enable: in std_logic;
-- High to re-seed the generator (requires enable = '1').
reseed: in std_logic; reseed: in std_logic;
-- New seed value (must be valid when reseed = '1'). -- New seed value (must be valid when reseed = '1').
newseed: in std_logic_vector(127 downto 0); newseed: in std_logic_vector(127 downto 0);
-- Output value. -- High when the user accepts the current random data word
-- A new value appears on every rising clock edge where enable = '1'. -- and requests new random data for the next clock cycle.
output: out std_logic_vector(63 downto 0) ); out_ready: in std_logic;
-- High when valid random data is available on the output.
-- This signal is low during the first clock cycle after reset and
-- after re-seeding, and high in all other cases.
out_valid: out std_logic;
-- Random output data (valid when out_valid = '1').
-- A new random word appears after every rising clock edge
-- where out_ready = '1'.
out_data: out std_logic_vector(63 downto 0) );
end entity; end entity;
architecture xoroshiro128plus_arch of xoroshiro128plus is architecture xoroshiro128plus_arch of rng_xoroshiro128plus is
-- Internal state of RNG. -- Internal state of RNG.
signal reg_state_s0: std_logic_vector(63 downto 0) := init_seed(63 downto 0); signal reg_state_s0: std_logic_vector(63 downto 0) := init_seed(63 downto 0);
signal reg_state_s1: std_logic_vector(63 downto 0) := init_seed(127 downto 64); signal reg_state_s1: std_logic_vector(63 downto 0) := init_seed(127 downto 64);
-- Output register. -- Output register.
signal reg_valid: std_logic;
signal reg_output: std_logic_vector(63 downto 0) := (others => '0'); signal reg_output: std_logic_vector(63 downto 0) := (others => '0');
-- Shift left. -- Shift left.
@ -105,16 +113,18 @@ architecture xoroshiro128plus_arch of xoroshiro128plus is
begin begin
-- Drive output signal. -- Drive output signal.
output <= reg_output; out_valid <= reg_valid;
out_data <= reg_output;
-- Synchronous process. -- Synchronous process.
process (clk) is process (clk) is
begin begin
if rising_edge(clk) then if rising_edge(clk) then
if enable = '1' then if out_ready = '1' or reg_valid = '0' then
-- Prepare output word. -- Prepare output word.
reg_valid <= '1';
reg_output <= std_logic_vector(unsigned(reg_state_s0) + reg_output <= std_logic_vector(unsigned(reg_state_s0) +
unsigned(reg_state_s1)); unsigned(reg_state_s1));
@ -128,18 +138,20 @@ begin
reg_state_s1 <= rotl(reg_state_s0, 36) xor reg_state_s1 <= rotl(reg_state_s0, 36) xor
rotl(reg_state_s1, 36); rotl(reg_state_s1, 36);
-- Re-seed function. end if;
if reseed = '1' then
reg_state_s0 <= newseed(63 downto 0);
reg_state_s1 <= newseed(127 downto 64);
end if;
-- Re-seed function.
if reseed = '1' then
reg_state_s0 <= newseed(63 downto 0);
reg_state_s1 <= newseed(127 downto 64);
reg_valid <= '0';
end if; end if;
-- Synchronous reset. -- Synchronous reset.
if rst = '1' then if rst = '1' then
reg_state_s0 <= init_seed(63 downto 0); reg_state_s0 <= init_seed(63 downto 0);
reg_state_s1 <= init_seed(127 downto 64); reg_state_s1 <= init_seed(127 downto 64);
reg_valid <= '0';
reg_output <= (others => '0'); reg_output <= (others => '0');
end if; end if;