Trivium: Fix bugs in testbench, add more test vectors.
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@ -24,12 +24,11 @@ architecture arch of tb_trivium is
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key: std_logic_vector(79 downto 0);
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iv: std_logic_vector(79 downto 0);
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data: output_vectors(0 to 3);
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-- data: array (0 to 3) of output_vector;
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end record;
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type test_vectors is array (natural range <>) of test_vector;
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constant testvec: test_vectors(0 to 1) := (
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constant testvec: test_vectors(0 to 4) := (
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0 => ( key => x"0053A6F94C9FF24598EB",
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iv => x"0D74DB42A91077DE45AC",
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data => ( ( pos => 0, data =>
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@ -73,7 +72,73 @@ architecture arch of tb_trivium is
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x"EBF14772061C210843C18CEA2D2A275A" &
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x"E02FCB18E5D7942455FF77524E8A4CA5" &
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x"1E369A847D1AEEFB9002FCD02342983C" &
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x"EAFA9D487CC2032B10192CD416310FA4" )))
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x"EAFA9D487CC2032B10192CD416310FA4" ))),
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2 => ( key => x"00000000000000000000",
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iv => x"00000000000000000000",
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data => ( ( pos => 0, data =>
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x"FBE0BF265859051B517A2E4E239FC97F" &
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x"563203161907CF2DE7A8790FA1B2E9CD" &
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x"F75292030268B7382B4C1A759AA2599A" &
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x"285549986E74805903801A4CB5A5D4F2" ),
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( pos => 192, data =>
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x"0F1BE95091B8EA857B062AD52BADF477" &
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x"84AC6D9B2E3F85A9D79995043302F0FD" &
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x"F8B76E5BC8B7B4F0AA46CD20DDA04FDD" &
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x"197BC5E1635496828F2DBFB23F6BD5D0" ),
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( pos => 256, data =>
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x"80F9075437BAC73F696D0ABE3972F5FC" &
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x"E2192E5FCC13C0CB77D0ABA09126838D" &
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x"31A2D38A2087C46304C8A63B54109F67" &
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x"9B0B1BC71E72A58D6DD3E0A3FF890D4A" ),
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( pos => 448, data =>
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x"68450EB0910A98EF1853E0FC1BED8AB6" &
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x"BB08DF5F167D34008C2A85284D4B886D" &
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x"D56883EE92BF18E69121670B4C81A568" &
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x"9C9B0538373D22EB923A28A2DB44C0EB" ))),
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3 => ( key => x"00000000000000000000",
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iv => x"80000000000000000000",
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data => ( ( pos => 0, data =>
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x"F8901736640549E3BA7D42EA2D07B9F4" &
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x"9233C18D773008BD755585B1A8CBAB86" &
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x"C1E9A9B91F1AD33483FD6EE3696D659C" &
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x"9374260456A36AAE11F033A519CBD5D7" ),
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( pos => 192, data =>
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x"87423582AF64475C3A9C092E32A53C5F" &
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x"E07D35B4C9CA288A89A43DEF3913EA92" &
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x"37CA43342F3F8E83AD3A5C38D463516F" &
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x"94E3724455656A36279E3E924D442F06" ),
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( pos => 256, data =>
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x"D94389A90E6F3BF2BB4C8B057339AAD8" &
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x"AA2FEA238C29FCAC0D1FF1CB2535A070" &
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x"58BA995DD44CFC54CCEC54A5405B944C" &
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x"532D74E50EA370CDF1BA1CBAE93FC0B5" ),
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( pos => 448, data =>
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x"4844151714E56A3A2BBFBA426A1D60F9" &
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x"A4F265210A91EC29259AE2035234091C" &
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x"49FFB1893FA102D425C57C39EB4916F6" &
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x"D148DC83EBF7DE51EEB9ABFE045FB282" ))),
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4 => ( key => x"0558ABFE51A4F74A9DF0",
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iv => x"167DE44BB21980E74EB5",
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data => ( ( pos => 0, data =>
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x"A850A970ABCF5F73BCC5DB76F6B5E856" &
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x"362F1B36AC498D05C20FBE7763598DE1" &
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x"FD98B03CC54060E8C9C19B16490C665C" &
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x"3636A03BAB46656A695ED75F0E659F04" ),
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( pos => 65472, data =>
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x"D5F687A689F19C4F2258E212C3FAD8BA" &
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x"68625155CC92A43F282BB0F2F6851D4B" &
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x"6E748CE6E0774590F9A6F38DD1DA63BB" &
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x"B1C977697A5CE4BABE127A1201AE7520" ),
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( pos => 65536, data =>
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x"FE6E274131503C78178A5678020DC3E2" &
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x"E151B621C9DFC0DE065EADB396A149CD" &
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x"FB92E0009ECFC50237C81B0067B07E0E" &
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x"794AF78468E88B9E472E723ABC73C21A" ),
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( pos => 131008, data =>
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x"85E6891E2A605CF81224112E596B40A6" &
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x"8C9D971AFC4376220B8160DCB36D55C0" &
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x"4B0C21AF68A2EC38B4145F32BEDCE260" &
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x"12CF2151D6768E4CD025114C5E3149A5" )))
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);
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signal clk: std_logic;
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@ -139,7 +204,8 @@ architecture arch of tb_trivium is
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signal s_newiv: out std_logic_vector(79 downto 0);
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signal s_ready: out std_logic;
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signal s_valid: in std_logic;
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signal s_data: in std_logic_vector)
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signal s_data: in std_logic_vector;
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variable num_errors: inout natural)
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is
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constant nbit: natural := s_data'length;
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constant init_duration: natural := 4 * 288 / nbit;
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@ -236,7 +302,7 @@ architecture arch of tb_trivium is
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write(lin, force_str("out["));
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write(lin, testvec(k).data(vk).pos, right, 6);
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write(lin, force_str("] = "));
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write(lin, to_hex_string(flipbits( w(127 downto 0))));
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write(lin, to_hex_string(flipbits(w(127 downto 0))));
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writeline(output, lin);
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for tk in 1 to w'length / 128 - 1 loop
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write(lin, force_str(" "));
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@ -248,6 +314,9 @@ architecture arch of tb_trivium is
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-- Check against expected output vector.
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assert w = flipbits(testvec(k).data(vk).data)
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report "Unexpected output from RNG";
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if w /= flipbits(testvec(k).data(vk).data) then
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num_errors := num_errors + 1;
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end if;
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-- Go to next output vector.
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vk := vk + 1;
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@ -270,8 +339,8 @@ begin
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inst_x1: entity work.rng_trivium
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generic map (
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num_bits => 1,
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init_key => x"eb9845f29f4cf9a65300",
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init_iv => x"ac45de7710a942db740d" )
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init_key => flipbits(testvec(0).key),
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init_iv => flipbits(testvec(0).iv) )
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port map (
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clk => clk,
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rst => x1_rst,
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@ -286,8 +355,8 @@ begin
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inst_x8: entity work.rng_trivium
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generic map (
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num_bits => 8,
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init_key => x"0053A6F94C9FF24598EB",
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init_iv => x"0D74DB42A91077DE45AC" )
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init_key => flipbits(testvec(0).key),
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init_iv => flipbits(testvec(0).iv) )
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port map (
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clk => clk,
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rst => x8_rst,
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@ -302,8 +371,8 @@ begin
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inst_x64: entity work.rng_trivium
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generic map (
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num_bits => 64,
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init_key => x"eb9845f29f4cf9a65300",
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init_iv => x"ac45de7710a942db740d" )
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init_key => flipbits(testvec(0).key),
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init_iv => flipbits(testvec(0).iv) )
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port map (
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clk => clk,
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rst => x64_rst,
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@ -319,6 +388,7 @@ begin
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-- Main simulation process.
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process is
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variable num_errors: natural := 0;
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begin
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report "Start test bench";
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@ -335,21 +405,24 @@ begin
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-- Test 1-bit instance.
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report "Test 1-bit generator";
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test_inst(x1_rst, x1_reseed, x1_newkey, x1_newiv,
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x1_out_ready, x1_out_valid, x1_out_data);
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x1_out_ready, x1_out_valid, x1_out_data, num_errors);
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-- Test 8-bit instance.
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report "Test 8-bit generator";
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test_inst(x8_rst, x8_reseed, x8_newkey, x8_newiv,
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x8_out_ready, x8_out_valid, x8_out_data);
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x8_out_ready, x8_out_valid, x8_out_data, num_errors);
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-- Test 64-bit instance.
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report "Test 64-bit generator";
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test_inst(x64_rst, x64_reseed, x64_newkey, x64_newiv,
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x64_out_ready, x64_out_valid, x64_out_data);
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x64_out_ready, x64_out_valid, x64_out_data, num_errors);
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-- End simulation.
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report "End testbench";
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assert num_errors = 0
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report "Errors detected in generator output";
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clock_active <= false;
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wait;
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