diff --git a/sim/tb_trivium.vhdl b/sim/tb_trivium.vhdl index 6dd31f8..df9e76f 100644 --- a/sim/tb_trivium.vhdl +++ b/sim/tb_trivium.vhdl @@ -24,12 +24,11 @@ architecture arch of tb_trivium is key: std_logic_vector(79 downto 0); iv: std_logic_vector(79 downto 0); data: output_vectors(0 to 3); --- data: array (0 to 3) of output_vector; end record; type test_vectors is array (natural range <>) of test_vector; - constant testvec: test_vectors(0 to 1) := ( + constant testvec: test_vectors(0 to 4) := ( 0 => ( key => x"0053A6F94C9FF24598EB", iv => x"0D74DB42A91077DE45AC", data => ( ( pos => 0, data => @@ -73,7 +72,73 @@ architecture arch of tb_trivium is x"EBF14772061C210843C18CEA2D2A275A" & x"E02FCB18E5D7942455FF77524E8A4CA5" & x"1E369A847D1AEEFB9002FCD02342983C" & - x"EAFA9D487CC2032B10192CD416310FA4" ))) + x"EAFA9D487CC2032B10192CD416310FA4" ))), + 2 => ( key => x"00000000000000000000", + iv => x"00000000000000000000", + data => ( ( pos => 0, data => + x"FBE0BF265859051B517A2E4E239FC97F" & + x"563203161907CF2DE7A8790FA1B2E9CD" & + x"F75292030268B7382B4C1A759AA2599A" & + x"285549986E74805903801A4CB5A5D4F2" ), + ( pos => 192, data => + x"0F1BE95091B8EA857B062AD52BADF477" & + x"84AC6D9B2E3F85A9D79995043302F0FD" & + x"F8B76E5BC8B7B4F0AA46CD20DDA04FDD" & + x"197BC5E1635496828F2DBFB23F6BD5D0" ), + ( pos => 256, data => + x"80F9075437BAC73F696D0ABE3972F5FC" & + x"E2192E5FCC13C0CB77D0ABA09126838D" & + x"31A2D38A2087C46304C8A63B54109F67" & + x"9B0B1BC71E72A58D6DD3E0A3FF890D4A" ), + ( pos => 448, data => + x"68450EB0910A98EF1853E0FC1BED8AB6" & + x"BB08DF5F167D34008C2A85284D4B886D" & + x"D56883EE92BF18E69121670B4C81A568" & + x"9C9B0538373D22EB923A28A2DB44C0EB" ))), + 3 => ( key => x"00000000000000000000", + iv => x"80000000000000000000", + data => ( ( pos => 0, data => + x"F8901736640549E3BA7D42EA2D07B9F4" & + x"9233C18D773008BD755585B1A8CBAB86" & + x"C1E9A9B91F1AD33483FD6EE3696D659C" & + x"9374260456A36AAE11F033A519CBD5D7" ), + ( pos => 192, data => + x"87423582AF64475C3A9C092E32A53C5F" & + x"E07D35B4C9CA288A89A43DEF3913EA92" & + x"37CA43342F3F8E83AD3A5C38D463516F" & + x"94E3724455656A36279E3E924D442F06" ), + ( pos => 256, data => + x"D94389A90E6F3BF2BB4C8B057339AAD8" & + x"AA2FEA238C29FCAC0D1FF1CB2535A070" & + x"58BA995DD44CFC54CCEC54A5405B944C" & + x"532D74E50EA370CDF1BA1CBAE93FC0B5" ), + ( pos => 448, data => + x"4844151714E56A3A2BBFBA426A1D60F9" & + x"A4F265210A91EC29259AE2035234091C" & + x"49FFB1893FA102D425C57C39EB4916F6" & + x"D148DC83EBF7DE51EEB9ABFE045FB282" ))), + 4 => ( key => x"0558ABFE51A4F74A9DF0", + iv => x"167DE44BB21980E74EB5", + data => ( ( pos => 0, data => + x"A850A970ABCF5F73BCC5DB76F6B5E856" & + x"362F1B36AC498D05C20FBE7763598DE1" & + x"FD98B03CC54060E8C9C19B16490C665C" & + x"3636A03BAB46656A695ED75F0E659F04" ), + ( pos => 65472, data => + x"D5F687A689F19C4F2258E212C3FAD8BA" & + x"68625155CC92A43F282BB0F2F6851D4B" & + x"6E748CE6E0774590F9A6F38DD1DA63BB" & + x"B1C977697A5CE4BABE127A1201AE7520" ), + ( pos => 65536, data => + x"FE6E274131503C78178A5678020DC3E2" & + x"E151B621C9DFC0DE065EADB396A149CD" & + x"FB92E0009ECFC50237C81B0067B07E0E" & + x"794AF78468E88B9E472E723ABC73C21A" ), + ( pos => 131008, data => + x"85E6891E2A605CF81224112E596B40A6" & + x"8C9D971AFC4376220B8160DCB36D55C0" & + x"4B0C21AF68A2EC38B4145F32BEDCE260" & + x"12CF2151D6768E4CD025114C5E3149A5" ))) ); signal clk: std_logic; @@ -139,7 +204,8 @@ architecture arch of tb_trivium is signal s_newiv: out std_logic_vector(79 downto 0); signal s_ready: out std_logic; signal s_valid: in std_logic; - signal s_data: in std_logic_vector) + signal s_data: in std_logic_vector; + variable num_errors: inout natural) is constant nbit: natural := s_data'length; constant init_duration: natural := 4 * 288 / nbit; @@ -236,7 +302,7 @@ architecture arch of tb_trivium is write(lin, force_str("out[")); write(lin, testvec(k).data(vk).pos, right, 6); write(lin, force_str("] = ")); - write(lin, to_hex_string(flipbits( w(127 downto 0)))); + write(lin, to_hex_string(flipbits(w(127 downto 0)))); writeline(output, lin); for tk in 1 to w'length / 128 - 1 loop write(lin, force_str(" ")); @@ -248,6 +314,9 @@ architecture arch of tb_trivium is -- Check against expected output vector. assert w = flipbits(testvec(k).data(vk).data) report "Unexpected output from RNG"; + if w /= flipbits(testvec(k).data(vk).data) then + num_errors := num_errors + 1; + end if; -- Go to next output vector. vk := vk + 1; @@ -270,8 +339,8 @@ begin inst_x1: entity work.rng_trivium generic map ( num_bits => 1, - init_key => x"eb9845f29f4cf9a65300", - init_iv => x"ac45de7710a942db740d" ) + init_key => flipbits(testvec(0).key), + init_iv => flipbits(testvec(0).iv) ) port map ( clk => clk, rst => x1_rst, @@ -286,8 +355,8 @@ begin inst_x8: entity work.rng_trivium generic map ( num_bits => 8, - init_key => x"0053A6F94C9FF24598EB", - init_iv => x"0D74DB42A91077DE45AC" ) + init_key => flipbits(testvec(0).key), + init_iv => flipbits(testvec(0).iv) ) port map ( clk => clk, rst => x8_rst, @@ -302,8 +371,8 @@ begin inst_x64: entity work.rng_trivium generic map ( num_bits => 64, - init_key => x"eb9845f29f4cf9a65300", - init_iv => x"ac45de7710a942db740d" ) + init_key => flipbits(testvec(0).key), + init_iv => flipbits(testvec(0).iv) ) port map ( clk => clk, rst => x64_rst, @@ -319,6 +388,7 @@ begin -- Main simulation process. process is + variable num_errors: natural := 0; begin report "Start test bench"; @@ -335,21 +405,24 @@ begin -- Test 1-bit instance. report "Test 1-bit generator"; test_inst(x1_rst, x1_reseed, x1_newkey, x1_newiv, - x1_out_ready, x1_out_valid, x1_out_data); + x1_out_ready, x1_out_valid, x1_out_data, num_errors); -- Test 8-bit instance. report "Test 8-bit generator"; test_inst(x8_rst, x8_reseed, x8_newkey, x8_newiv, - x8_out_ready, x8_out_valid, x8_out_data); + x8_out_ready, x8_out_valid, x8_out_data, num_errors); -- Test 64-bit instance. report "Test 64-bit generator"; test_inst(x64_rst, x64_reseed, x64_newkey, x64_newiv, - x64_out_ready, x64_out_valid, x64_out_data); + x64_out_ready, x64_out_valid, x64_out_data, num_errors); -- End simulation. report "End testbench"; + assert num_errors = 0 + report "Errors detected in generator output"; + clock_active <= false; wait;