359 lines
13 KiB
VHDL
359 lines
13 KiB
VHDL
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--
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-- Test bench for PRNG Trivium.
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--
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use std.textio.all;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity tb_trivium is
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end entity;
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architecture arch of tb_trivium is
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type output_vector is record
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pos: natural;
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data: std_logic_vector(511 downto 0);
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end record;
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type output_vectors is array (natural range <>) of output_vector;
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type test_vector is record
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key: std_logic_vector(79 downto 0);
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iv: std_logic_vector(79 downto 0);
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data: output_vectors(0 to 3);
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-- data: array (0 to 3) of output_vector;
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end record;
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type test_vectors is array (natural range <>) of test_vector;
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constant testvec: test_vectors(0 to 1) := (
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0 => ( key => x"0053A6F94C9FF24598EB",
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iv => x"0D74DB42A91077DE45AC",
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data => ( ( pos => 0, data =>
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x"F4CD954A717F26A7D6930830C4E7CF08" &
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x"19F80E03F25F342C64ADC66ABA7F8A8E" &
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x"6EAA49F23632AE3CD41A7BD290A0132F" &
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x"81C6D4043B6E397D7388F3A03B5FE358" ),
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( pos => 65472, data =>
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x"C04C24A6938C8AF8A491D5E481271E0E" &
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x"601338F01067A86A795CA493AA4FF265" &
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x"619B8D448B706B7C88EE8395FC79E5B5" &
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x"1AB40245BBF7773AE67DF86FCFB71F30" ),
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( pos => 65536, data =>
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x"011A0D7EC32FA102C66C164CFCB189AE" &
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x"D9F6982E8C7370A6A37414781192CEB1" &
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x"55C534C1C8C9E53FDEADF2D3D0577DAD" &
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x"3A8EB2F6E5265F1E831C86844670BC69" ),
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( pos => 131008, data =>
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x"48107374A9CE3AAF78221AE77789247C" &
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x"F6896A249ED75DCE0CF2D30EB9D889A0" &
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x"C61C9F480E5C07381DED9FAB2AD54333" &
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x"E82C89BA92E6E47FD828F1A66A8656E0" ))),
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1 => ( key => x"80000000000000000000",
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iv => x"00000000000000000000",
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data => ( ( pos => 0, data =>
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x"38EB86FF730D7A9CAF8DF13A4420540D" &
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x"BB7B651464C87501552041C249F29A64" &
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x"D2FBF515610921EBE06C8F92CECF7F80" &
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x"98FF20CCCC6A62B97BE8EF7454FC80F9" ),
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( pos => 192, data =>
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x"EAF2625D411F61E41F6BAEEDDD5FE202" &
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x"600BD472F6C9CD1E9134A745D900EF6C" &
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x"023E4486538F09930CFD37157C0EB57C" &
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x"3EF6C954C42E707D52B743AD83CFF297" ),
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( pos => 256, data =>
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x"9A203CF7B2F3F09C43D188AA13A5A202" &
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x"1EE998C42F777E9B67C3FA221A0AA1B0" &
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x"41AA9E86BC2F5C52AFF11F7D9EE480CB" &
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x"1187B20EB46D582743A52D7CD080A24A" ),
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( pos => 448, data =>
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x"EBF14772061C210843C18CEA2D2A275A" &
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x"E02FCB18E5D7942455FF77524E8A4CA5" &
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x"1E369A847D1AEEFB9002FCD02342983C" &
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x"EAFA9D487CC2032B10192CD416310FA4" )))
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);
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signal clk: std_logic;
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signal clock_active: boolean := false;
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signal x1_rst: std_logic;
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signal x1_reseed: std_logic;
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signal x1_newkey: std_logic_vector(79 downto 0);
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signal x1_newiv: std_logic_vector(79 downto 0);
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signal x1_out_ready: std_logic;
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signal x1_out_valid: std_logic;
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signal x1_out_data: std_logic_vector(0 downto 0);
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signal x8_rst: std_logic;
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signal x8_reseed: std_logic;
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signal x8_newkey: std_logic_vector(79 downto 0);
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signal x8_newiv: std_logic_vector(79 downto 0);
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signal x8_out_ready: std_logic;
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signal x8_out_valid: std_logic;
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signal x8_out_data: std_logic_vector(7 downto 0);
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signal x64_rst: std_logic;
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signal x64_reseed: std_logic;
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signal x64_newkey: std_logic_vector(79 downto 0);
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signal x64_newiv: std_logic_vector(79 downto 0);
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signal x64_out_ready: std_logic;
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signal x64_out_valid: std_logic;
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signal x64_out_data: std_logic_vector(63 downto 0);
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-- Convert bit vector to hexadecimal string.
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function to_hex_string(s: std_logic_vector)
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return string
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is
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constant alphabet: string(1 to 16) := "0123456789abcdef";
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variable y: string(1 to s'length/4);
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begin
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for i in y'range loop
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y(i) := alphabet(to_integer(unsigned(s(s'high+4-4*i downto s'high+1-4*i))) + 1);
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end loop;
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return y;
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end function;
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-- Reverse order of 8-bit groups within long bit vector.
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function flipbits(x: std_logic_vector) return std_logic_vector is
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variable y: std_logic_vector(x'length-1 downto 0);
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begin
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for p in 0 to x'length / 8 - 1 loop
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y(p*8+7 downto p*8) := x(x'high-p*8 downto x'high-p*8-7);
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end loop;
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return y;
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end function;
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-- Force interpretation of string literal.
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function force_str(s: string) return string is
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begin
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return s;
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end function;
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-- Test one of the instances of the RNG.
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procedure test_inst(signal s_rst: out std_logic;
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signal s_reseed: out std_logic;
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signal s_newkey: out std_logic_vector(79 downto 0);
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signal s_newiv: out std_logic_vector(79 downto 0);
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signal s_ready: out std_logic;
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signal s_valid: in std_logic;
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signal s_data: in std_logic_vector)
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is
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constant nbit: natural := s_data'length;
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constant init_duration: natural := 4 * 288 / nbit;
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variable lin: line;
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variable p: natural := 0;
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variable bitpos: natural;
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variable vk: natural;
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variable w: std_logic_vector(511 downto 0);
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variable wp: natural;
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begin
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-- Initialize inputs.
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s_reseed <= '0';
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s_newkey <= (others => '0');
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s_newiv <= (others => '0');
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s_ready <= '0';
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-- End reset.
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wait until falling_edge(clk);
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s_rst <= '0';
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-- Loop over test vectors.
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for k in testvec'range loop
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write(lin, force_str("key = "));
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write(lin, to_hex_string(testvec(k).key));
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writeline(output, lin);
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write(lin, force_str("iv = "));
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write(lin, to_hex_string(testvec(k).iv));
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writeline(output, lin);
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-- Reseed generator, except for first test vector.
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-- First test vector runs on initial seed.
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if k /= 0 then
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s_reseed <= '1';
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s_newkey <= flipbits(testvec(k).key);
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s_newiv <= flipbits(testvec(k).iv);
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wait until falling_edge(clk);
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s_reseed <= '0';
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s_newkey <= (others => '0');
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s_newiv <= (others => '0');
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end if;
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-- Give generator time to complete initialization.
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for i in 0 to init_duration loop
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assert s_valid = '0'
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report "Generator indicates VALID too early";
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if (p mod 3 = 0) or (p mod 5 = 0) or (p mod 17 = 0) then
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s_ready <= '0';
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else
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s_ready <= '1';
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end if;
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wait until falling_edge(clk);
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p := p + 1;
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end loop;
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-- Start generating random bits.
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bitpos := 0;
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-- Start looping over output vectors.
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vk := testvec(k).data'low;
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while vk <= testvec(k).data'high loop
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-- Generate a block of bits.
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assert s_valid = '1' report "Output not VALID";
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if (p mod 3 = 0) or (p mod 5 = 0) or (p mod 17 = 0) then
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-- Skipping this clock cycle.
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s_ready <= '0';
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else
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-- Consuming data this clock cycle.
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s_ready <= '1';
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if bitpos >= testvec(k).data(vk).pos * 8 then
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-- Store bits in block.
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wp := bitpos - testvec(k).data(vk).pos * 8;
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assert wp = 0 or wp >= nbit
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report "Invalid test vector offset";
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assert wp + nbit <= w'length
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report "Invalid test vector offset";
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w(wp+nbit-1 downto wp) := s_data;
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end if;
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bitpos := bitpos + nbit;
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end if;
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wait until falling_edge(clk);
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p := p + 1;
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if bitpos = testvec(k).data(vk).pos * 8 + w'length then
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-- Reached end of current output vector.
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-- Dump output data to screen.
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write(lin, force_str("out["));
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write(lin, testvec(k).data(vk).pos, right, 6);
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write(lin, force_str("] = "));
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write(lin, to_hex_string(flipbits( w(127 downto 0))));
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writeline(output, lin);
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for tk in 1 to w'length / 128 - 1 loop
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write(lin, force_str(" "));
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write(lin, to_hex_string(flipbits(
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w(128*tk+127 downto 128*tk))));
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writeline(output, lin);
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end loop;
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-- Check against expected output vector.
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assert w = flipbits(testvec(k).data(vk).data)
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report "Unexpected output from RNG";
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-- Go to next output vector.
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vk := vk + 1;
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end if;
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end loop;
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-- Go to next test vector.
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writeline(output, lin);
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end loop;
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-- Put instance back in reset.
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s_rst <= '1';
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end procedure;
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begin
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-- Instantiate PRNG with 1-bit output.
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inst_x1: entity work.rng_trivium
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generic map (
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num_bits => 1,
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init_key => x"eb9845f29f4cf9a65300",
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init_iv => x"ac45de7710a942db740d" )
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port map (
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clk => clk,
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rst => x1_rst,
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reseed => x1_reseed,
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newkey => x1_newkey,
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newiv => x1_newiv,
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out_ready => x1_out_ready,
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out_valid => x1_out_valid,
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out_data => x1_out_data );
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-- Instantiate PRNG with 8-bit output.
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inst_x8: entity work.rng_trivium
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generic map (
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num_bits => 8,
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init_key => x"0053A6F94C9FF24598EB",
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init_iv => x"0D74DB42A91077DE45AC" )
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port map (
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clk => clk,
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rst => x8_rst,
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reseed => x8_reseed,
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newkey => x8_newkey,
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newiv => x8_newiv,
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out_ready => x8_out_ready,
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out_valid => x8_out_valid,
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out_data => x8_out_data );
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-- Instantiate PRNG with 64-bit output.
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inst_x64: entity work.rng_trivium
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generic map (
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num_bits => 64,
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init_key => x"eb9845f29f4cf9a65300",
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init_iv => x"ac45de7710a942db740d" )
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port map (
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clk => clk,
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rst => x64_rst,
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reseed => x64_reseed,
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newkey => x64_newkey,
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newiv => x64_newiv,
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out_ready => x64_out_ready,
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out_valid => x64_out_valid,
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out_data => x64_out_data );
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-- Generate clock.
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clk <= (not clk) after 10 ns when clock_active else '0';
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-- Main simulation process.
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process is
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begin
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report "Start test bench";
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-- Reset all instances.
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x1_rst <= '1';
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x8_rst <= '1';
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x64_rst <= '1';
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-- Start clock.
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clock_active <= true;
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wait for 30 ns;
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-- Test 1-bit instance.
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report "Test 1-bit generator";
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test_inst(x1_rst, x1_reseed, x1_newkey, x1_newiv,
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x1_out_ready, x1_out_valid, x1_out_data);
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-- Test 8-bit instance.
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report "Test 8-bit generator";
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test_inst(x8_rst, x8_reseed, x8_newkey, x8_newiv,
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x8_out_ready, x8_out_valid, x8_out_data);
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-- Test 64-bit instance.
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report "Test 64-bit generator";
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test_inst(x64_rst, x64_reseed, x64_newkey, x64_newiv,
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x64_out_ready, x64_out_valid, x64_out_data);
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-- End simulation.
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report "End testbench";
|
||
|
|
|
||
|
|
clock_active <= false;
|
||
|
|
wait;
|
||
|
|
|
||
|
|
end process;
|
||
|
|
|
||
|
|
end architecture;
|